fsgnjx.s

Floating-Point Sign-Inject XOR Single-Precision

The fsgnjx.s instruction produces a result that takes all bits except the sign bit from fs1. The result’s sign bit is the XOR of sign bits of fs1 and fs2, and the result is written to the destination register fd. Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs.

This instruction must have data-independent timing when extension Zkt is enabled.

Assembly format

fsgnjx.s fd, fs1, fs2

Decode Variables

Bits<5> fs2 = $encoding[24:20];
Bits<5> fs1 = $encoding[19:15];
Bits<5> fd = $encoding[11:7];

Execution

  • IDL

  • Sail

check_f_ok($encoding);
Bits<32> sp_value = {f[fs1][31] ^ f[fs2][31], f[fs1][30:0]};
if (implemented?(ExtensionName::D)) {
  f[fd] = nan_box<32, 64>(sp_value);
} else {
  f[fd] = sp_value;
}
mark_f_state_dirty();
{
  let rs1_val_S = F_or_X_S(rs1);
  let rs2_val_S = F_or_X_S(rs2);

  let (fflags, rd_val) : (bits_fflags, bool) =
      riscv_f32Le (rs1_val_S, rs2_val_S);

  accrue_fflags(fflags);
  X(rd) = zero_extend(bool_to_bits(rd_val));
  RETIRE_SUCCESS
}

Exceptions

This instruction may result in the following synchronous exceptions:

  • IllegalInstruction

Encoding

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Defining extension

F, version >= F@2.2.0

Access

M

Always

Containing profiles

  • Mandatory: RVA20S64, RVA20U64, RVA22S64, RVA22U64, RVA23M64, RVA23S64, RVA23U64, RVB23M64, RVB23S64, RVB23U64

  • Optional: RVI20U32, RVI20U64