aes64es

AES encrypt final round

Assembly format

aes64es rd, rs1, rs2

Synopsis

This instruction must have data-independent timing when extension Zkt is enabled.

Uses the two 64-bit source registers to represent the entire AES state, and produces half of the next round output, applying the ShiftRows and SubBytes steps.

Decode Variables

Bits<5> rs2 = $encoding[24:20];
Bits<5> rs1 = $encoding[19:15];
Bits<5> rd = $encoding[11:7];

Execution

  • IDL

Encoding

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Defining extension

  • Zkne, version >= Zkne@1.0.0

Access

M HS U VS VU

Always

Always

Always

Always

Always

Containing profiles

  • Mandatory:

  • Optional: RVA22S64, RVA22U64, RVA23M64, RVA23S64, RVB23M64, RVB23S64, RVB23U64