mstateen0

Machine State Enable 0 Register

Each bit of a stateen CSR controls less-privileged access to an extension’s state, or an extension that was not deemed "worthy" of a full XS field in sstatus like the FS and VS fields for the F and V extensions.

The number of registers provided at each level is four because it is believed that 4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for supervisor level, will be adequate for many years to come, perhaps for as long as the RISC-V ISA is in use. The exact number four is an attempted compromise between providing too few bits on the one hand and going overboard with CSRs that will never be used on the other.

The stateen registers at each level control access to state at all less-privileged levels, but not at its own level.

When a stateen CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. In some cases, the bits of the stateen CSRs will have a dual purpose as enables for the ISA extensions that introduce the controlled state.

For every bit with a defined purpose in an sstateen CSR, the same bit is defined in the matching mstateen CSR to control access below machine level to the same state. The upper 32 bits of an mstateen CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently inaccessible to user level, so no corresponding enable bits in the supervisor-level sstateen CSR are applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63, through to bit 32, and then on to the next-higher mstateen CSR. If the rate that bits are being allocated from the least-significant end for sstateen CSRs is sufficiently low, allocation from the most-significant end of mstateen CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher mstateen CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in the matching sstateen CSRs.

For every bit in an mstateen CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in the matching hstateen and sstateen CSRs.

A bit in a supervisor-level sstateen CSR cannot be read-only one unless the same bit is read-only one in the matching mstateen CSR and, if it exists, in the matching hstateen CSR. A bit in an hstateen CSR cannot be read-only one unless the same bit is read-only one in the matching mstateen CSR. Bit 63 of each mstateen CSR may be read-only zero only if the hypervisor extension is not implemented and the matching supervisor-level sstateen CSR is all read-only zeros.

Attributes

Defining Extension

  • Smstateen, version >= Smstateen@1.0.0

CSR Address

0x30c

Length

64-bit

Privilege Mode

M

Format

mstateen0 format
Figure 1. mstateen0 format

Field Summary

Name Location Type Reset Value

mstateen0.SE0

63

RW

0

mstateen0.ENVCFG

62

RW

0

mstateen0.CSRIND

60

RW

0

mstateen0.AIA

59

RW

0

mstateen0.IMSIC

58

RW

0

mstateen0.CONTEXT

57

RW

0

mstateen0.P1P13

56

RW

0

mstateen0.SRMCFG

55

RW

0

mstateen0.CTR

54

RW

0

mstateen0.JVT

2

RW

0

mstateen0.FCSR

1

RW

0

mstateen0.C

0

RW

0

Fields

SE0

Location

63

Description

The SE0 bit in mstateen0 controls access to the hstateen0, hstateen0h, and the sstateen0 CSRs.

Type

RW

Reset value

0

ENVCFG

Location

62

Description

The ENVCFG bit in mstateen0 controls access to the henvcfg, henvcfgh, and the senvcfg CSRs.

Type

RW

Reset value

0

CSRIND

Location

60

Description

The CSRIND bit in mstateen0 controls access to the siselect, sireg*, vsiselect, and the vsireg* CSRs provided by the Sscsrind extensions.

Type

RW

Reset value

0

AIA

Location

59

Description

The AIA bit in mstateen0 controls access to all state introduced by the Ssaia extension and is not controlled by either the CSRIND or the IMSIC bits.

Type

RW

Reset value

0

IMSIC

Location

58

Description

The IMSIC bit in mstateen0 controls access to the IMSIC state, including CSRs stopei and vstopei, provided by the Ssaia extension.

Type

RW

Reset value

0

CONTEXT

Location

57

Description

The CONTEXT bit in mstateen0 controls access to the scontext and hcontext CSRs provided by the Sdtrig extension.

Type

RW

Reset value

0

P1P13

Location

56

Description

The P1P13 bit in mstateen0 controls access to the hedelegh introduced by Privileged Specification Version 1.13.

Type

RW

Reset value

0

SRMCFG

Location

55

Description

The SRMCFG bit in mstateen0 controls access to the srmcfg` CSR introduced by the Ssqosid Chapter 18 extension.

Type

RW

Reset value

0

CTR

Location

54

Description

When Smstateen is implemented, the mstateen0.CTR bit controls access to CTR register state from privilege modes less privileged than M-mode.

Type

RW

Reset value

0

JVT

Location

2

Description

The JVT bit controls access to the jvt CSR provided by the Zcmt extension.

Type

RW

Reset value

0

FCSR

Location

1

Description

The FCSR bit controls access to fcsr for the case when floating-point instructions operate on x registers instead of f registers as specified by the Zfinx and related extensions (Zdinx, etc.). Whenever misa.F = 1, FCSR bit of mstateen0 is read-only zero (and hence read-only zero in hstateen0 and sstateen0 too). For convenience, when the stateen CSRs are implemented and misa.F = 0, then if the FCSR bit of a controlling stateen0 CSR is zero, all floating-point instructions cause an illegal instruction trap (or virtual instruction trap, if relevant), as though they all access fcsr, regardless of whether they really do.

Type

RW

Reset value

0

C

Location

0

Description

The C bit controls access to any and all custom state. The C bit of these registers is not custom state itself; it is a standard field of a standard CSR, either mstateen0, hstateen0, or sstateen0.

Type

RW

Reset value

0