scountovf
Supervisor Count Overflow
A 32-bit read-only register that contains shadow copies of the OF bits in the 29 mhpmevent CSRs
(mhpmevent3 - mhpmevent31) — where scountovf bit X corresponds to mhpmeventX.
This register enables supervisor-level overflow interrupt handler software to quickly and easily determine which counter(s) have overflowed without needing to make an execution environment call up to M-mode.
Read access to bit X is subject to the same mcounteren (or mcounteren and hcounteren)
CSRs that mediate access to the hpmcounter CSRs by S-mode (or VS-mode).
In M-mode, scountovf bit X is always readable. In S/HS-mode, scountovf bit X is readable when mcounteren bit X is set, and otherwise reads as zero. Similarly, in VS-mode, it is readable when both mcounteren and hcounteren bit X are set.
Attributes
Defining Extension |
|
|---|---|
CSR Address |
0xda0 |
Length |
32-bit |
Privilege Mode |
S |
Field Summary
| Name | Location | Type | Reset Value |
|---|---|---|---|
3 |
[when,"HPM_COUNTER_EN[3]"] RO [when,"!(HPM_COUNTER_EN[3])"] RO-H |
UNDEFINED_LEGAL |
|
4 |
[when,"HPM_COUNTER_EN[4]"] RO [when,"!(HPM_COUNTER_EN[4])"] RO-H |
UNDEFINED_LEGAL |
|
5 |
[when,"HPM_COUNTER_EN[5]"] RO [when,"!(HPM_COUNTER_EN[5])"] RO-H |
UNDEFINED_LEGAL |
|
6 |
[when,"HPM_COUNTER_EN[6]"] RO [when,"!(HPM_COUNTER_EN[6])"] RO-H |
UNDEFINED_LEGAL |
|
7 |
[when,"HPM_COUNTER_EN[7]"] RO [when,"!(HPM_COUNTER_EN[7])"] RO-H |
UNDEFINED_LEGAL |
|
8 |
[when,"HPM_COUNTER_EN[8]"] RO [when,"!(HPM_COUNTER_EN[8])"] RO-H |
UNDEFINED_LEGAL |
|
9 |
[when,"HPM_COUNTER_EN[9]"] RO [when,"!(HPM_COUNTER_EN[9])"] RO-H |
UNDEFINED_LEGAL |
|
10 |
[when,"HPM_COUNTER_EN[10]"] RO [when,"!(HPM_COUNTER_EN[10])"] RO-H |
UNDEFINED_LEGAL |
|
11 |
[when,"HPM_COUNTER_EN[11]"] RO [when,"!(HPM_COUNTER_EN[11])"] RO-H |
UNDEFINED_LEGAL |
|
12 |
[when,"HPM_COUNTER_EN[12]"] RO [when,"!(HPM_COUNTER_EN[12])"] RO-H |
UNDEFINED_LEGAL |
|
13 |
[when,"HPM_COUNTER_EN[13]"] RO [when,"!(HPM_COUNTER_EN[13])"] RO-H |
UNDEFINED_LEGAL |
|
14 |
[when,"HPM_COUNTER_EN[14]"] RO [when,"!(HPM_COUNTER_EN[14])"] RO-H |
UNDEFINED_LEGAL |
|
15 |
[when,"HPM_COUNTER_EN[15]"] RO [when,"!(HPM_COUNTER_EN[15])"] RO-H |
UNDEFINED_LEGAL |
|
16 |
[when,"HPM_COUNTER_EN[16]"] RO [when,"!(HPM_COUNTER_EN[16])"] RO-H |
UNDEFINED_LEGAL |
|
17 |
[when,"HPM_COUNTER_EN[17]"] RO [when,"!(HPM_COUNTER_EN[17])"] RO-H |
UNDEFINED_LEGAL |
|
18 |
[when,"HPM_COUNTER_EN[18]"] RO [when,"!(HPM_COUNTER_EN[18])"] RO-H |
UNDEFINED_LEGAL |
|
19 |
[when,"HPM_COUNTER_EN[19]"] RO [when,"!(HPM_COUNTER_EN[19])"] RO-H |
UNDEFINED_LEGAL |
|
20 |
[when,"HPM_COUNTER_EN[20]"] RO [when,"!(HPM_COUNTER_EN[20])"] RO-H |
UNDEFINED_LEGAL |
|
21 |
[when,"HPM_COUNTER_EN[21]"] RO [when,"!(HPM_COUNTER_EN[21])"] RO-H |
UNDEFINED_LEGAL |
|
22 |
[when,"HPM_COUNTER_EN[22]"] RO [when,"!(HPM_COUNTER_EN[22])"] RO-H |
UNDEFINED_LEGAL |
|
23 |
[when,"HPM_COUNTER_EN[23]"] RO [when,"!(HPM_COUNTER_EN[23])"] RO-H |
UNDEFINED_LEGAL |
|
24 |
[when,"HPM_COUNTER_EN[24]"] RO [when,"!(HPM_COUNTER_EN[24])"] RO-H |
UNDEFINED_LEGAL |
|
25 |
[when,"HPM_COUNTER_EN[25]"] RO [when,"!(HPM_COUNTER_EN[25])"] RO-H |
UNDEFINED_LEGAL |
|
26 |
[when,"HPM_COUNTER_EN[26]"] RO [when,"!(HPM_COUNTER_EN[26])"] RO-H |
UNDEFINED_LEGAL |
|
27 |
[when,"HPM_COUNTER_EN[27]"] RO [when,"!(HPM_COUNTER_EN[27])"] RO-H |
UNDEFINED_LEGAL |
|
28 |
[when,"HPM_COUNTER_EN[28]"] RO [when,"!(HPM_COUNTER_EN[28])"] RO-H |
UNDEFINED_LEGAL |
|
29 |
[when,"HPM_COUNTER_EN[29]"] RO [when,"!(HPM_COUNTER_EN[29])"] RO-H |
UNDEFINED_LEGAL |
|
30 |
[when,"HPM_COUNTER_EN[30]"] RO [when,"!(HPM_COUNTER_EN[30])"] RO-H |
UNDEFINED_LEGAL |
|
31 |
[when,"HPM_COUNTER_EN[31]"] RO [when,"!(HPM_COUNTER_EN[31])"] RO-H |
UNDEFINED_LEGAL |
Software read
This CSR may return a value that is different from what is stored in hardware.
Bits<32> mask;
if (mode() == PrivilegeMode::VS) {
mask = $bits(mcounteren) & $bits(hcounteren);
} else {
mask = $bits(mcounteren) & $bits(scounteren);
}
Bits<32> value = 0;
value = value | (mhpmevent3.OF << 3);
value = value | (mhpmevent4.OF << 4);
value = value | (mhpmevent5.OF << 5);
value = value | (mhpmevent6.OF << 6);
value = value | (mhpmevent7.OF << 7);
value = value | (mhpmevent8.OF << 8);
value = value | (mhpmevent9.OF << 9);
value = value | (mhpmevent10.OF << 10);
value = value | (mhpmevent11.OF << 11);
value = value | (mhpmevent12.OF << 12);
value = value | (mhpmevent13.OF << 13);
value = value | (mhpmevent14.OF << 14);
value = value | (mhpmevent15.OF << 15);
value = value | (mhpmevent16.OF << 16);
value = value | (mhpmevent17.OF << 17);
value = value | (mhpmevent18.OF << 18);
value = value | (mhpmevent19.OF << 19);
value = value | (mhpmevent20.OF << 20);
value = value | (mhpmevent21.OF << 21);
value = value | (mhpmevent22.OF << 22);
value = value | (mhpmevent23.OF << 23);
value = value | (mhpmevent24.OF << 24);
value = value | (mhpmevent25.OF << 25);
value = value | (mhpmevent26.OF << 26);
value = value | (mhpmevent27.OF << 27);
value = value | (mhpmevent28.OF << 28);
value = value | (mhpmevent29.OF << 29);
value = value | (mhpmevent30.OF << 30);
value = value | (mhpmevent31.OF << 31);
return value & mask;