aes64im :: RISC-V ISA Manual

Assembly format

aes64im rd, rs1

Synopsis

This instruction must have data-independent timing when extension Zkt is enabled.

The instruction applies the inverse MixColumns transformation to two columns of the state array, packed into a single 64-bit register. It is used to create the inverse cipher KeySchedule, according to the equivalent inverse cipher construction in (NIST, 2001) (Page 23, Section 5.3.5).

Decode Variables

Bits<5> rs1 = $encoding[19:15];
Bits<5> rd = $encoding[11:7];

Execution

IDL

Encoding

Defining extension

Zknd, version >= Zknd@1.0.0

Access

M	HS	U	VS	VU
Always	Always	Always	Always	Always

M

HS

U

VS

VU

Always

Containing profiles

Mandatory:
Optional: RVA22S64, RVA22U64, RVA23M64, RVA23S64, RVB23M64, RVB23S64, RVB23U64