henvcfgh

most-significant 32 bits of Hypervisor Environment Configuration

The henvcfgh CSR is a 32-bit read/write register for the most-significant 32 bits of henvcfg.

Attributes

Defining Extension

  • allOf:

    • Sm, version >=1.12

    • H, version >= H@1.0.0

CSR Address

0x61a

Length

32-bit

Privilege Mode

S

Format

henvcfgh format
Figure 1. henvcfgh format

Field Summary

Name Location Type Reset Value

henvcfgh.STCE

31

[when,"implemented?(ExtensionName::Sstc)"] RO

[when,"!(implemented?(ExtensionName::Sstc))"] RW

UNDEFINED_LEGAL

henvcfgh.PBMTE

30

[when,"implemented?(ExtensionName::Svpbmt)"] RO

[when,"!(implemented?(ExtensionName::Svpbmt))"] RW

UNDEFINED_LEGAL

henvcfgh.ADUE

29

[when,"implemented?(ExtensionName::Svadu)"] RO

[when,"!(implemented?(ExtensionName::Svadu))"] RW

UNDEFINED_LEGAL

Fields

STCE

Location

31

Description

STimecmp Enable

When set, stimecmp is operational in VS-mode if menvcfg.STCE is also set.

When menvcfg.STCE is zero: * henvcfg.STCE reads-as-zero * vstimecmp access raises an IllegalInstruction exception. * hip.VSTIP reverts to its defined behavior as if Sstc is not implemented. * VS-mode timer interrupts will not be generated

When menvcfg.STCE is one and henvcfg.STCE is zero: * Accessing stimecmp in VS-mode or VU-mode (really vstimecmp) raises a VirtualInterrupt exception * hip.VSTIP reverts to its defined behavior as if Sstc is not implemented. * VS-mode timer interrupts will not be generated

Type
RO
RW
Reset value

UNDEFINED_LEGAL

PBMTE

Location

30

Description

Page Based Memory Type Enable

The PBMTE bit controls whether the Svpbmt extension is available for use in VS-stage address translation.

When PBMTE=1, Svpbmt is available for VS-stage address translation.

When PBMTE=0, the implementation behaves as though Svpbmt were not implemented for VS-stage address translation.

If Svpbmt is not implemented, PBMTE is read-only zero.

henvcfg.PBMTE is read-as-zero if menvcfg.PBMTE is zero.

If the setting of the PBMTE bit in menvcfg is changed, an hfence.gvma instruction with rs1=x0 and rs2=x0 suffices to synchronize with respect to the altered interpretation of G-stage and VS-stage PTEs' PBMT fields.

By contrast, if the PBMTE bit in henvcfg is changed, executing an hfence.vvma with rs1=x0 and rs2=x0 suffices to synchronize with respect to the altered interpretation of VS-stage PTEs' PBMT fields for the currently active VMID.

No mechanism is provided to atomically change vsatp and hgatp together. Hence, to prevent speculative execution causing one guest’s VS-stage translations to be cached under another guest’s VMID, world-switch code should zero vsatp, then swap hgatp, then finally write the new vsatp value. Similarly, if henvcfg.PBMTE need be world-switched, it should be switched after zeroing vsatp but before writing the new vsatp value, obviating the need to execute an hfence.vvma instruction.
Type
RO
RW
Reset value

UNDEFINED_LEGAL

ADUE

Location

29

Description

If the Svadu extension is implemented, the ADUE bit controls whether hardware updating of PTE A/D bits is enabled for VS-stage address translation.

When ADUE=1, hardware updating of PTE A/D bits is enabled during VS-stage address translation, and the implementation behaves as though the Svade extension were not implemented for VS-mode address translation.

When ADUE=0, the implementation behaves as though Svade were implemented for VS-stage address translation.

If Svadu is not implemented, ADUE is read-only zero.

Furthermore, for implementations with the hypervisor extension, henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero.

Type
RO
RW
Reset value

UNDEFINED_LEGAL

Software read

This CSR may return a value that is different from what is stored in hardware.

return henvcfg.sw_read()[63:32];