Zcmp Extension

Versions

1.0.0
State

ratified

Ratification date

2023-04

Synopsis

The Zcmp extension is a set of instructions which may be executed as a series of existing 32-bit RISC-V instructions.

This extension reuses some encodings from c.fsdsp. Therefore it is incompatible with [Zcd], which is included when C and D extensions are both present.

Zcmp is primarily targeted at embedded class CPUs due to implementation complexity. Additionally, it is not compatible with architecture class profiles.

The Zcmp extension depends on the [Zca] extension.

The PUSH/POP assembly syntax uses several variables, the meaning of which are:

  • reg_list is a list containing 1 to 13 registers (ra and 0 to 12 s registers)

    • valid values: {ra}, {ra, s0}, {ra, s0-s1}, {ra, s0-s2}, …​, {ra, s0-s8}, {ra, s0-s9}, {ra, s0-s11}

    • note that {ra, s0-s10} is not valid, giving 12 lists not 13 for better encoding

  • stack_adj is the total size of the stack frame.

    • valid values vary with register list length and the specific encoding, see the instruction pages for details.

RV32 RV64 Mnemonic Instruction

yes

yes

cm.push {reg_list}, -stack_adj

[insns-cm_push]

yes

yes

cm.pop {reg_list}, stack_adj

[insns-cm_pop]

yes

yes

cm.popret {reg_list}, stack_adj

[insns-cm_popret]

yes

yes

cm.popretz {reg_list}, stack_adj

[insns-cm_popretz]

yes

yes

cm.mva01s rs1', rs2'

[insns-cm_mva01s]

yes

yes

cm.mvsa01 r1s', r2s'

[insns-cm_mvsa01]