sraiw

Shift right arithmetic immediate word

Arithmetic shift (the original sign bit is copied into the vacated upper bits) the 32-bit value in xs1 right by shamt, and store the sign-extended result in xd.

This instruction must have data-independent timing when extension Zkt is enabled.

Assembly format

sraiw rd, rs1, shamt

Decode Variables

Bits<5> shamt = $encoding[24:20];
Bits<5> xs1 = $encoding[19:15];
Bits<5> xd = $encoding[11:7];

Execution

IDL
Sail

XReg operand = sext(X[xs1], 31);
X[xd] = sext(operand >>> shamt, 31);

{
  let xs1_val = (X(xs1))[31..0];
  let result : bits(32) = match op {
    RISCV_SLLIW => xs1_val << shamt,
    RISCV_SRLIW => xs1_val >> shamt,
    RISCV_SRAIW => shift_right_arith32(xs1_val, shamt)
  };
  X(xd) = sign_extend(result);
  RETIRE_SUCCESS
}

Encoding

Defining extension

I, version >= I@2.1.0

Access

M	HS	U	VS	VU
Always	Always	Always	Always	Always

Always

Containing profiles

Mandatory: MockProfile 64-bit S-mode, MockProfile 64-bit Unpriv, RVA20S64, RVA20U64, RVA22S64, RVA22U64, RVA23M64, RVA23S64, RVA23U64, RVB23M64, RVB23S64, RVB23U64, RVI20U32, RVI20U64
Optional: