bclr

Single-Bit clear (Register)

This instruction is defined by:

  • anyOf:

    • B, version >= B@1.0.0

    • Zbs, version >= Zbs@1.0.0

This instruction is included in the following profiles:

  • RVA22U64 (Mandatory)

  • RVA23U64 (Mandatory)

  • RVB23U64 (Mandatory)

Encoding

svg

Assembly format

bclr rd, rs1, rs2

Synopsis

This instruction returns rs1 with a single bit cleared at the index specified in rs2. The index is read from the lower log2(XLEN) bits of rs2.

Access

M HS U VS VU

Always

Always

Always

Always

Always

Decode Variables

Bits<5> rs2 = $encoding[24:20];
Bits<5> rs1 = $encoding[19:15];
Bits<5> rd = $encoding[11:7];
idl

Execution

if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
  raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
}
XReg index = X[rs2] & (xlen() - 1);
X[rd] = X[rs1] & ~(1 << index);
idl

Exceptions

This instruction may result in the following synchronous exceptions:

  • IllegalInstruction