bclr

Single-Bit clear (Register)

This instruction is defined by:

  • Zbs, version >= Zbs@1.0.0

This instruction is included in the following profiles:

  • RVA22S64 (Mandatory)

  • RVA22U64 (Mandatory)

  • RVA23M64 (Mandatory)

  • RVA23S64 (Mandatory)

  • RVA23U64 (Mandatory)

  • RVB23M64 (Mandatory)

  • RVB23S64 (Mandatory)

  • RVB23U64 (Mandatory)

Encoding

svg

Assembly format

bclr rd, rs1, rs2

Synopsis

This instruction returns rs1 with a single bit cleared at the index specified in rs2. The index is read from the lower log2(XLEN) bits of rs2.

Access

M HS U VS VU

Always

Always

Always

Always

Always

Decode Variables

Bits<5> rs2 = $encoding[24:20];
Bits<5> rs1 = $encoding[19:15];
Bits<5> rd = $encoding[11:7];

Execution

  • IDL

  • Sail

if (%%LINK%func;implemented?;implemented?%%(ExtensionName::B) && (%%LINK%csr_field;misa.B;CSR[misa].B%% == 1'b0)) {
  %%LINK%func;raise;raise%%(ExceptionCode::IllegalInstruction, %%LINK%func;mode;mode%%(), $encoding);
}
XReg index = X[rs2] & (%%LINK%func;xlen;xlen%%() - 1);
X[rd] = X[rs1] & ~(1 << index);
{
  let rs1_val = X(rs1);
  let rs2_val = X(rs2);
  let mask : xlenbits = if sizeof(xlen) == 32
                        then zero_extend(0b1) << rs2_val[4..0]
                        else zero_extend(0b1) << rs2_val[5..0];
  let result : xlenbits = match op {
    RISCV_BCLR => rs1_val & ~(mask),
    RISCV_BEXT => zero_extend(bool_to_bits((rs1_val & mask) != zeros())),
    RISCV_BINV => rs1_val ^ mask,
    RISCV_BSET => rs1_val | mask
  };
  X(rd) = result;
  RETIRE_SUCCESS
}

Exceptions

This instruction may result in the following synchronous exceptions:

  • IllegalInstruction