pmpcfg11

PMP Configuration Register 11

PMP entry configuration

Attributes

Defining Extension

  • Smpmp, version >= 0

CSR Address

0x3ab

Length

32-bit

Privilege Mode

M

Format

pmpcfg11 format
Figure 1. pmpcfg11 format

Field Summary

Name Location Type Reset Value

pmpcfg11.pmp44cfg

7:0

[when,"(NUM_PMP_ENTRIES > 44)"] RW-R [when,"(NUM_PMP_ENTRIES ⇐ 44)"] RO

[when,"(NUM_PMP_ENTRIES > 44)"] UNDEFINED_LEGAL [when,"(NUM_PMP_ENTRIES ⇐ 44)"] 0

pmpcfg11.pmp45cfg

15:8

[when,"(NUM_PMP_ENTRIES > 45)"] RW-R [when,"(NUM_PMP_ENTRIES ⇐ 45)"] RO

[when,"(NUM_PMP_ENTRIES > 45)"] UNDEFINED_LEGAL [when,"(NUM_PMP_ENTRIES ⇐ 45)"] 0

pmpcfg11.pmp46cfg

23:16

[when,"(NUM_PMP_ENTRIES > 46)"] RW-R [when,"(NUM_PMP_ENTRIES ⇐ 46)"] RO

[when,"(NUM_PMP_ENTRIES > 46)"] UNDEFINED_LEGAL [when,"(NUM_PMP_ENTRIES ⇐ 46)"] 0

pmpcfg11.pmp47cfg

31:24

[when,"(NUM_PMP_ENTRIES > 47)"] RW-R [when,"(NUM_PMP_ENTRIES ⇐ 47)"] RO

[when,"(NUM_PMP_ENTRIES > 47)"] UNDEFINED_LEGAL [when,"(NUM_PMP_ENTRIES ⇐ 47)"] 0

Fields

pmp44cfg

Location

7:0

Description

PMP configuration for entry 44

The bits are as follows:

Name Location Description

L

7

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

6:5

Reserved Writes shall be ignored.

A

4:3

Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NA4* (2) - Naturally aligned four-byte region
* *NAPOT* (3) - Naturally aligned power of two
[when="PMP_GRANULARITY >= 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NAPOT* (3) - Naturally aligned power of two

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

X

2

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

1

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

0

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type
RW-R
RO
Reset value
UNDEFINED_LEGAL
0

pmp45cfg

Location

15:8

Description

PMP configuration for entry 45

The bits are as follows:

Name Location Description

L

15

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

14:13

Reserved Writes shall be ignored.

A

12:11

Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NA4* (2) - Naturally aligned four-byte region
* *NAPOT* (3) - Naturally aligned power of two
[when="PMP_GRANULARITY >= 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NAPOT* (3) - Naturally aligned power of two

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

X

10

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

9

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

8

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type
RW-R
RO
Reset value
UNDEFINED_LEGAL
0

pmp46cfg

Location

23:16

Description

PMP configuration for entry 46

The bits are as follows:

Name Location Description

L

23

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

22:21

Reserved Writes shall be ignored.

A

20:19

Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NA4* (2) - Naturally aligned four-byte region
* *NAPOT* (3) - Naturally aligned power of two
[when="PMP_GRANULARITY >= 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NAPOT* (3) - Naturally aligned power of two

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

X

18

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

17

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

16

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type
RW-R
RO
Reset value
UNDEFINED_LEGAL
0

pmp47cfg

Location

31:24

Description

PMP configuration for entry 47

The bits are as follows:

Name Location Description

L

31

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

30:29

Reserved Writes shall be ignored.

A

28:27

Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NA4* (2) - Naturally aligned four-byte region
* *NAPOT* (3) - Naturally aligned power of two
[when="PMP_GRANULARITY >= 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NAPOT* (3) - Naturally aligned power of two

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

X

26

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

25

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

24

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type
RW-R
RO
Reset value
UNDEFINED_LEGAL
0

Software write

This CSR may store a value that is different from what software attempts to write.

When a software write occurs (e.g., through csrrw), the following determines the written value:

pmp44cfg = if ((CSR[pmpcfg11].pmp44cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp44cfg & 0x1) == 0) && ((csr_value.pmp44cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp44cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp44cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg11].pmp44cfg;

pmp45cfg = if ((CSR[pmpcfg11].pmp45cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp45cfg & 0x1) == 0) && ((csr_value.pmp45cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp45cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp45cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg11].pmp45cfg;

pmp46cfg = if ((CSR[pmpcfg11].pmp46cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp46cfg & 0x1) == 0) && ((csr_value.pmp46cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp46cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp46cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg11].pmp46cfg;

pmp47cfg = if ((CSR[pmpcfg11].pmp47cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp47cfg & 0x1) == 0) && ((csr_value.pmp47cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp47cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp47cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg11].pmp47cfg;