misa :: RISC-V ISA Manual

Attributes

Defining Extension	Sm, version >= 0
CSR Address	0x301
Length	32 when CSR[misa].MXL == 0 64 when CSR[misa].MXL == 1
Privilege Mode	M

Defining Extension

Sm, version >= 0

CSR Address

0x301

Length

32 when CSR[misa].MXL == 0 64 when CSR[misa].MXL == 1

Privilege Mode

M

Format

This CSR format changes dynamically.

Figure 1. misa Format when CSR[misa].MXL == 0

Figure 2. misa Format when CSR[misa].MXL == 1

Field Summary

Name	Location	Type	Reset Value
misa.MXL	* 31:30 when CSR[misa].MXL == 0 * 63:62 when CSR[misa].MXL == 1	RO	2
misa.A	0	[when,"implemented?(ExtensionName::A) && MUTABLE_MISA_A"] RW [when,"!implemented?(ExtensionName::A) && MUTABLE_MISA_A"] RO	1
misa.B	1	[when,"implemented?(ExtensionName::B) && MUTABLE_MISA_B"] RW [when,"!implemented?(ExtensionName::B) && MUTABLE_MISA_B"] RO	1
misa.C	2	[when,"implemented?(ExtensionName::C) && MUTABLE_MISA_C"] RW [when,"!implemented?(ExtensionName::C) && MUTABLE_MISA_C"] RO	1
misa.D	3	[when,"implemented?(ExtensionName::D) && MUTABLE_MISA_D"] RW [when,"!implemented?(ExtensionName::D) && MUTABLE_MISA_D"] RO	1
misa.F	5	[when,"implemented?(ExtensionName::F) && MUTABLE_MISA_F"] RW [when,"!implemented?(ExtensionName::F) && MUTABLE_MISA_F"] RO	1
misa.G	6	[when,"(((implemented?(ExtensionName::A) && MUTABLE_MISA_A \|\| implemented?(ExtensionName::M) && MUTABLE_MISA_M) \|\| implemented?(ExtensionName::F) && MUTABLE_MISA_F) \|\| implemented?(ExtensionName::D) && MUTABLE_MISA_D)"] RO-H [when,"!(((implemented?(ExtensionName::A) && MUTABLE_MISA_A \|\| implemented?(ExtensionName::M) && MUTABLE_MISA_M) \|\| implemented?(ExtensionName::F) && MUTABLE_MISA_F) \|\| implemented?(ExtensionName::D) && MUTABLE_MISA_D)"] RO	[when,"implemented?(ExtensionName::A) && implemented?(ExtensionName::M) && implemented?(ExtensionName::F) && implemented?(ExtensionName::D)"] 1 [when,"!implemented?(ExtensionName::A) && implemented?(ExtensionName::M) && implemented?(ExtensionName::F) && implemented?(ExtensionName::D)"] 0
misa.H	7	[when,"implemented?(ExtensionName::H) && MUTABLE_MISA_H"] RW [when,"!implemented?(ExtensionName::H) && MUTABLE_MISA_H"] RO	1
misa.I	8	RO	1
misa.M	13	[when,"implemented?(ExtensionName::M) && MUTABLE_MISA_M"] RW [when,"!implemented?(ExtensionName::M) && MUTABLE_MISA_M"] RO	1
misa.S	19	[when,"implemented?(ExtensionName::S) && MUTABLE_MISA_S"] RW [when,"!implemented?(ExtensionName::S) && MUTABLE_MISA_S"] RO	1
misa.U	21	[when,"implemented?(ExtensionName::U) && MUTABLE_MISA_U"] RW [when,"!implemented?(ExtensionName::U) && MUTABLE_MISA_U"] RO	1
misa.V	22	RO	1

Fields

`MXL`

Location

31:30 when CSR[misa].MXL == 0
63:62 when CSR[misa].MXL == 1

Description

XLEN in M-mode.

Type

RO

Reset value

2

A

Location: 0
Description: Indicates support for the A (atomic) extension.

Writing 0 to this field will cause all atomic instructions to raise an IllegalInstruction exception.

Type

RW

RO

Reset value: 1

B

Location: 1
Description: Indicates support for the B (bitmanip) extension.

Writing 0 to this field will cause all bitmanip instructions to raise an IllegalInstruction exception.

Type

RW

RO

Reset value: 1

C

Location: 2
Description: Indicates support for the C (compressed) extension.

Writing 0 to this field will cause all compressed instructions to raise an IllegalInstruction exception. Additionally, IALIGN becomes 32.

Type

RW

RO

Reset value: 1

D

Location: 3
Description: Indicates support for the D (double precision float) extension.

Writing 0 to this field will cause all double-precision floating point instructions to raise an IllegalInstruction exception.

Additionally, the upper 32-bits of the f registers will read as zero.

Type

RW

RO

Reset value: 1

F

Location: 5
Description: Indicates support for the F (single precision float) extension.

Writing 0 to this field will cause all floating point (single and double precision) instructions to raise an IllegalInstruction exception.

Writing 0 to this field with misa.D set will result in UNDEFINED behavior.

Type

RW

RO

Reset value: 1

`G`

Location: 6
Description: Indicates support for all of the following extensions: I, A, M, F, D.
Type

RO-H

RO

Reset value

1

0

H

Location: 7
Description: Indicates support for the H (hypervisor) extension.

Writing 0 to this field will cause all attempts to enter VS- or VU- mode, execute a hypervisor instruction, or access a hypervisor CSR to raise an IllegalInstruction fault.

Type

RW

RO

Reset value: 1

I

Location: 8
Description: Indicates support for the I (base) extension.
Type: RO
Reset value: 1

M

Location: 13
Description: Indicates support for the M (integer multiply/divide) extension.

Writing 0 to this field will cause all attempts to execute an integer multiply or divide instruction to raise an IllegalInstruction exception.

Type

RW

RO

Reset value: 1

S

Location: 19
Description: Indicates support for the S (supervisor mode) extension.

Writing 0 to this field will cause all attempts to enter S-mode or access S-mode state to raise an exception.

Type

RW

RO

Reset value: 1

U

Location: 21
Description: Indicates support for the U (user mode) extension.

Writing 0 to this field will cause all attempts to enter U-mode to raise an exception.

Type

RW

RO

Reset value: 1

V

Location: 22
Description: Indicates support for the V (vector) extension.

Writing 0 to this field will cause all attempts to execute a vector instruction to raise an IllegalInstruction trap.

Type: RO
Reset value: 1

Software write

This CSR may store a value that is different from what software attempts to write.

When a software write occurs (e.g., through csrrw), the following determines the written value:

MXL = csr_value.MXL
A = csr_value.A
B = csr_value.B
C = csr_value.C
D = csr_value.D
F = if (csr_value.F == 0 && csr_value.D == 1) {
  return UNDEFINED_LEGAL_DETERMINISTIC;
}

# fall-through; write the intended value
return csr_value.F;

G = csr_value.G
H = csr_value.H
I = csr_value.I
M = csr_value.M
S = csr_value.S
U = csr_value.U
V = csr_value.V

Software read

This CSR may return a value that is different from what is stored in hardware.

return ((CSR[misa].MXL << 62) | (CSR[misa].V << 21) | (CSR[misa].U << 20) | (CSR[misa].S << 18) | (CSR[misa].M << 12) | (CSR[misa].I << 7) | (CSR[misa].H << 6) | ((CSR[misa].A & CSR[misa].M & CSR[misa].F & CSR[misa].D) << 5) | (CSR[misa].F << 4) | (CSR[misa].D << 3) | (CSR[misa].C << 2) | (CSR[misa].B << 1) | CSR[misa].A);