mnepc
Machine Exception Program Counter
Written with the PC of an instruction on an exception or interrupt taken in M-mode.
Also controls where the hart jumps on an exception return from M-mode.
Attributes
Requirement |
|||
|---|---|---|---|
Defining extensions |
|
||
CSR Address |
0x741 |
||
Length |
* 32 when CSR[misa].MXL == 0 * 64 when CSR[misa].MXL == 1 |
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Privilege Mode |
M |
Format
This CSR format changes dynamically.
Field Summary
| Name | Location | Type | Reset Value |
|---|---|---|---|
* 31:0 when CSR[misa].MXL == 0 * 63:0 when CSR[misa].MXL == 1 |
RW-RH |
UNDEFINED_LEGAL |
Fields
PC
- Location
-
-
31:0 when CSR[misa].MXL == 0
-
63:0 when CSR[misa].MXL == 1
-
- Description
-
When a NMI / double trap is taken into M-mode, mnepc.PC is written with the virtual address of the instruction that was interrupted or that encountered the exception. Otherwise, mnepc.PC is never written by the implementation, though it may be explicitly written by software.
On an exception return from M-mode NMI / double trap (from the MNRET instruction), control transfers to the virtual address read out of mnepc.PC.
Because PCs are always halfword-aligned, bit 0 of mnepc.PC is always read-only 0.
Because PCs are always word-aligned, bits 1:0 of mnepc.PC are always read-only 0.
When misa.C is clear, bit 1 is masked to zero. Writes to bit 1 are still captured, and may be visible on the next read with misa.C is set.
- Type
-
RW-RH
- Reset value
-
UNDEFINED_LEGAL
Software write
This CSR may store a value that is different from what software attempts to write.
When a software write occurs (e.g., through csrrw), the following determines the written value:
PC = return csr_value.PC & ~64'b1;