aes32dsmi

AES middle round decryption instruction for RV32

Sources a single byte from rs2 according to bs. To this it applies the inverse AES SBox operation, and a partial inverse MixColumn, before XOR’ing the result with rs1. This instruction must always be implemented such that its execution latency does not depend on the data being operated on.

This instruction must have data-independent timing when extension Zkt is enabled.

Assembly format

aes32dsmi rd, rs1, rs2, bs

Decode Variables

Bits<2> bs = $encoding[31:30];
Bits<5> rs2 = $encoding[24:20];
Bits<5> rs1 = $encoding[19:15];
Bits<5> rd = $encoding[11:7];

Execution

  • IDL

Encoding

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Defining extension

  • Zknd, version >= Zknd@1.0.0

Access

M HS U VS VU

Always

Always

Always

Always

Always

Containing profiles

  • Mandatory:

  • Optional: RVA22S64, RVA22U64, RVA23M64, RVA23S64, RVB23M64, RVB23S64, RVB23U64