aes32dsmi :: RISC-V ISA Manual

Assembly format

aes32dsmi rd, rs1, rs2, bs

Synopsis

This instruction must have data-independent timing when extension Zkt is enabled.

This instruction sources a single byte from rs2 according to bs. To this it applies the inverse AES SBox operation, and a partial inverse MixColumn, before XOR’ing the result with rs1. This instruction must always be implemented such that its execution latency does not depend on the data being operated on.

Decode Variables

Bits<2> bs = $encoding[31:30];
Bits<5> rs2 = $encoding[24:20];
Bits<5> rs1 = $encoding[19:15];
Bits<5> rd = $encoding[11:7];

Execution

IDL

Encoding

Defining extension

Zknd, version >= Zknd@1.0.0

Access

M	HS	U	VS	VU
Always	Always	Always	Always	Always

M

HS

U

VS

VU

Always

Containing profiles

Mandatory:
Optional: RVA22S64, RVA22U64, RVA23M64, RVA23S64, RVB23M64, RVB23S64, RVB23U64