mstateen0h
Upper 32 bits of Machine State Enable 0 Register
For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State Enable 0), mstateen1, mstateen2, and mstateen3. For RV32, the registers listed above are 32-bit, and for the machine-level CSRs there is a corresponding set of high-half CSRs for the upper 32 bits of each register: mstateen0h, mstateen1h, mstateen2h, mstateen3h.
Attributes
Defining Extension |
|
---|---|
CSR Address |
0x31c |
Length |
32-bit |
Privilege Mode |
M |
Field Summary
Name | Location | Type | Reset Value |
---|---|---|---|
31 |
RW |
0 |
|
30 |
RW |
0 |
|
28 |
RW |
0 |
|
27 |
RW |
0 |
|
26 |
RW |
0 |
|
25 |
RW |
0 |
|
24 |
RW |
0 |
|
23 |
RW |
0 |
|
22 |
RW |
0 |
Software write
This CSR may store a value that is different from what software attempts to write.
When a software write occurs (e.g., through csrrw), the following determines the written value:
SE0 = CSR[mstateen0].SE0 = csr_value.SE0; return csr_value.SE0; ENVCFG = CSR[mstateen0].ENVCFG = csr_value.ENVCFG; return csr_value.ENVCFG; CSRIND = CSR[mstateen0].CSRIND = csr_value.CSRIND; return csr_value.CSRIND; AIA = CSR[mstateen0].AIA = csr_value.AIA; return csr_value.AIA; IMSIC = CSR[mstateen0].IMSIC = csr_value.IMSIC; return csr_value.IMSIC; CONTEXT = CSR[mstateen0].CONTEXT = csr_value.CONTEXT; return csr_value.CONTEXT; P1P13 = CSR[mstateen0].P1P13 = csr_value.P1P13; return csr_value.P1P13; SRMCFG = CSR[mstateen0].SRMCFG = csr_value.SRMCFG; return csr_value.SRMCFG; CTR = CSR[mstateen0].CTR = csr_value.CTR; return csr_value.CTR;
Software read
This CSR may return a value that is different from what is stored in hardware.
return $bits(mstateen0)[63:32];