mstateen0h

Upper 32 bits of Machine State Enable 0 Register

For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State Enable 0), mstateen1, mstateen2, and mstateen3. For RV32, the registers listed above are 32-bit, and for the machine-level CSRs there is a corresponding set of high-half CSRs for the upper 32 bits of each register: mstateen0h, mstateen1h, mstateen2h, mstateen3h.

Attributes

Defining Extension

  • Smstateen, version >= Smstateen@1.0.0

CSR Address

0x31c

Length

32-bit

Privilege Mode

M

Format

mstateen0h format
Figure 1. mstateen0h format

Field Summary

Name Location Type Reset Value

mstateen0h.SE0

31

RW

0

mstateen0h.ENVCFG

30

RW

0

mstateen0h.CSRIND

28

RW

0

mstateen0h.AIA

27

RW

0

mstateen0h.IMSIC

26

RW

0

mstateen0h.CONTEXT

25

RW

0

mstateen0h.P1P13

24

RW

0

mstateen0h.SRMCFG

23

RW

0

mstateen0h.CTR

22

RW

0

Fields

SE0

Location

31

Description

The SE0 bit in mstateen0h controls access to the hstateen0, hstateen0h, and the sstateen0 CSRs.

Type

RW

Reset value

0

ENVCFG

Location

30

Description

The ENVCFG bit in mstateen0h controls access to the henvcfg, henvcfgh, and the senvcfg CSRs.

Type

RW

Reset value

0

CSRIND

Location

28

Description

The CSRIND bit in mstateen0h controls access to the siselect, sireg*, vsiselect, and the vsireg* CSRs provided by the Sscsrind extensions.

Type

RW

Reset value

0

AIA

Location

27

Description

The AIA bit in mstateen0h controls access to all state introduced by the Ssaia extension and is not controlled by either the CSRIND or the IMSIC bits.

Type

RW

Reset value

0

IMSIC

Location

26

Description

The IMSIC bit in mstateen0h controls access to the IMSIC state, including CSRs stopei and vstopei, provided by the Ssaia extension.

Type

RW

Reset value

0

CONTEXT

Location

25

Description

The CONTEXT bit in mstateen0h controls access to the scontext and hcontext CSRs provided by the Sdtrig extension.

Type

RW

Reset value

0

P1P13

Location

24

Description

The P1P13 bit in mstateen0h controls access to the hedelegh introduced by Privileged Specification Version 1.13.

Type

RW

Reset value

0

SRMCFG

Location

23

Description

The SRMCFG bit in mstateen0h controls access to the srmcfg` CSR introduced by the Ssqosid Chapter 18 extension.

Type

RW

Reset value

0

CTR

Location

22

Description

When Smstateen is implemented, the mstateen0.CTR bit controls access to CTR register state from privilege modes less privileged than M-mode.

Type

RW

Reset value

0

Software write

This CSR may store a value that is different from what software attempts to write.

When a software write occurs (e.g., through csrrw), the following determines the written value:

SE0 = CSR[mstateen0].SE0 = csr_value.SE0;
return csr_value.SE0;

ENVCFG = CSR[mstateen0].ENVCFG = csr_value.ENVCFG;
return csr_value.ENVCFG;

CSRIND = CSR[mstateen0].CSRIND = csr_value.CSRIND;
return csr_value.CSRIND;

AIA = CSR[mstateen0].AIA = csr_value.AIA;
return csr_value.AIA;

IMSIC = CSR[mstateen0].IMSIC = csr_value.IMSIC;
return csr_value.IMSIC;

CONTEXT = CSR[mstateen0].CONTEXT = csr_value.CONTEXT;
return csr_value.CONTEXT;

P1P13 = CSR[mstateen0].P1P13 = csr_value.P1P13;
return csr_value.P1P13;

SRMCFG = CSR[mstateen0].SRMCFG = csr_value.SRMCFG;
return csr_value.SRMCFG;

CTR = CSR[mstateen0].CTR = csr_value.CTR;
return csr_value.CTR;

Software read

This CSR may return a value that is different from what is stored in hardware.

return $bits(mstateen0)[63:32];