hstatus

Hypervisor Status

The hstatus register tracks and controls a VS-mode guest.

Unlike fields in sstatus, which are all aliases of fields mstatus, bits in hstatus are independent bits and do not have aliases.

Attributes

Defining Extension	H, version >= 0
CSR Address	0x600
Length	32 when CSR[mstatus].SXL == 0 64 when CSR[mstatus].SXL == 1
Privilege Mode	S

Defining Extension

H, version >= 0

CSR Address

0x600

Length

32 when CSR[mstatus].SXL == 0 64 when CSR[mstatus].SXL == 1

Privilege Mode

Format

This CSR format changes dynamically.

Figure 1. hstatus Format when CSR[mstatus].SXL == 0

Figure 2. hstatus Format when CSR[mstatus].SXL == 1

Field Summary

Name	Location	Type	Reset Value
hstatus.VSXL	33:32	[when,"(VSXLEN == 32 \|\| VSXLEN == 64)"] RO [when,"!(VSXLEN == 32 \|\| VSXLEN == 64)"] RW	[when,"(VSXLEN == 32)"] 0 [when,"(VSXLEN == 64)"] 1 [when,"else"] UNDEFINED_LEGAL
hstatus.VTSR	22	RW	UNDEFINED_LEGAL
hstatus.VTW	21	RW	UNDEFINED_LEGAL
hstatus.VTVM	20	RW	UNDEFINED_LEGAL
hstatus.VGEIN	17:12	[when,"(NUM_EXTERNAL_GUEST_INTERRUPTS == 63)"] RW [when,"(NUM_EXTERNAL_GUEST_INTERRUPTS != 63)"] RW-R	UNDEFINED_LEGAL
hstatus.HU	9	RW	UNDEFINED_LEGAL
hstatus.SPVP	8	RW	UNDEFINED_LEGAL
hstatus.SPV	7	RW	UNDEFINED_LEGAL
hstatus.GVA	6	RW	UNDEFINED_LEGAL
hstatus.VSBE	5	[when,"(VS_MODE_ENDIANESS == "dynamic")"] RW [when,"(VS_MODE_ENDIANESS != "dynamic")"] RO	[when,"(VS_MODE_ENDIANESS == "little")"] 0 [when,"(VS_MODE_ENDIANESS == "big")"] 1 [when,"else"] UNDEFINED_LEGAL

Name

Location

Type

Reset Value

hstatus.VSXL

33:32

[when,"(VSXLEN == 32 || VSXLEN == 64)"] RO [when,"!(VSXLEN == 32 || VSXLEN == 64)"] RW

[when,"(VSXLEN == 32)"] 0 [when,"(VSXLEN == 64)"] 1 [when,"else"] UNDEFINED_LEGAL

UNDEFINED_LEGAL

UNDEFINED_LEGAL

UNDEFINED_LEGAL

17:12

[when,"(NUM_EXTERNAL_GUEST_INTERRUPTS == 63)"] RW [when,"(NUM_EXTERNAL_GUEST_INTERRUPTS != 63)"] RW-R

UNDEFINED_LEGAL

UNDEFINED_LEGAL

UNDEFINED_LEGAL

UNDEFINED_LEGAL

UNDEFINED_LEGAL

[when,"(VS_MODE_ENDIANESS == "dynamic")"] RW [when,"(VS_MODE_ENDIANESS != "dynamic")"] RO

[when,"(VS_MODE_ENDIANESS == "little")"] 0 [when,"(VS_MODE_ENDIANESS == "big")"] 1 [when,"else"] UNDEFINED_LEGAL

Fields

`VSXL`

Location: 33:32
Description: VS-mode XLen

Determines the effective XLEN in VS-mode. Valid values are:

Value

VSXLEN

Because the implementation only supports a single VSXLEN == 32, this field is read-only-0.

Because the implementation only supports a single VSXLEN == 64, this field is read-only-1.

Type

Reset value

UNDEFINED_LEGAL

`VTSR`

Location: 22
Description: Virtual Trap SRET

When hstatus.VTSR is set, executing the sret instruction in VS-mode raises a Virtual Instruction exception.

When hstatus.VTSR is clear, an sret instruction in VS-mode returns control to the mode stored in vsstatus.SPP.

Type: RW
Reset value: UNDEFINED_LEGAL

`VTW`

Location: 21
Description: Virtual Trap WFI

When hstatus.VTW is set, a wfi instruction executed in VS-mode raises a Virtual Instruction exception after waiting an implementation-defined amount of time (which can be 0).

When both hstatus.VTW and mstatus.TW are clear, a wfi instruction executes in VS-mode without a timeout period.

The wfi instruction is also affected by mstatus.TW, as shown below:

mstatus.TW	hstatus.VTW	wfi behavior
HS-mode	U-mode	VS-mode	VU-mode
0	0	Wait	Trap (I)	Wait	Trap (V)
0	1	Wait	Trap (I)	Trap (V)	Trap (V)
1	-	Trap (I)	Trap (I)	Trap (I)	Trap (I)
Trap (I) - Trap with `Illegal Instruction` code Trap (V) - Trap with `Virtual Instruction` code

mstatus.TW

hstatus.VTW

wfi behavior

HS-mode

U-mode

VS-mode

VU-mode

Wait

Trap (I)

Wait

Trap (V)

Wait

Trap (I)

Trap (V)

Trap (I)

Trap (I) - Trap with Illegal Instruction code
Trap (V) - Trap with Virtual Instruction code

Type: RW
Reset value: UNDEFINED_LEGAL

`VTVM`

Location: 20
Description: Virtual Trap Virtual Memory

When set, a 'Virtual Instruction` trap occurs when executing an sfence.vma, sinval.vma, or an explicit CSR access of the satp (really vsatp) register when in VS-mode.

When clear, the instructions execute as normal in VS-mode.

Notably, hstatus.VTVM does not cause hfence.vvma, sfence.w.inval, or sfence.inval.ir to trap.

mstatus.TVM does not affect the VS-mode instructions controlled by hstatus.

Type: RW
Reset value: UNDEFINED_LEGAL

`VGEIN`

Location: 17:12
Description: Virtual Guest External Interrupt Number

Selects the guest external interrupt source for VS-level external interrupts.

When hstatus.VGEIN == 0, no external interrupt source is selected.

When hstatus.VGEIN != 0, it selects which bit of hgeip is currently active in VS-mode.

Type

RW-R

Reset value: UNDEFINED_LEGAL

`HU`

Location: 9
Description: Hypervisor in U-mode

When set, the hypervisor load/store instructions (hlv, hlvx, and hsv) can be executed in U-mode.

When clear, the hypervisor load/store instructions cause an Illegal Instruction trap.

Type: RW
Reset value: UNDEFINED_LEGAL

`SPVP`

Location: 8
Description: Supervisor Previous Virtual Privilege

Written by hardware:

When taking a trap into HS-mode from VS-mode or VU-mode, hstatus.SPVP is written with the nominal privilege mode

Notably, unlike its analog mstatus.SPP, hstatus.SPVP is not cleared when returning from a trap.

Can also be written by software without immediate side-effect.

Affects execution by:

Controls the effective privilege level applied to the hypervisor load/store instructions, hlv, hlvx, and hsv.

Type

RW

Reset value

UNDEFINED_LEGAL

`SPV`

Location: 7
Description: Supervisor Previous Virtualization Mode

Written by hardware:

On a trap into HS-mode, hardware writes 1 when the prior mode was VS-mode or VU-mode, and 0 otherwise.

Can also be written by software without immediate side-effect.

Affects execution by:

When an sret instruction in executed in HS-mode or M-mode, control returns to VS-mode or VU-mode (as selected by mstatus.SPP) when hstatus.SPV is 1 and to HS-mode or U-mode otherwise.

Type

RW

Reset value

UNDEFINED_LEGAL

`GVA`

Location: 6
Description: Guest Virtual Address

Written by hardware whenever a trap is taken into HS-mode:

Writes 1 when a trap causes a guest virtual address to be written into stval (Breakpoint, * Address Misaligned, * Access Fault, * Page Fault, or * Guest-Page Fault).
Writes 0 otherwise

Does not affect execution.

Type: RW
Reset value: UNDEFINED_LEGAL

`VSBE`

Location: 5
Description: VS-mode Big Endian

Controls the endianness of data VS-mode (0 = little, 1 = big). Instructions are always little endian, regardless of the data setting.

Since the CPU does not support big endian in VS-mode, this is hardwired to 0.

Since the CPU does not support little endian in VS-mode, this is hardwired to 1.

Type

Reset value

UNDEFINED_LEGAL

Software write

This CSR may store a value that is different from what software attempts to write.

When a software write occurs (e.g., through csrrw), the following determines the written value:

VSXL = if (CSR[mstatus].SXL < csr_value.VSXL) {
  # cannot set VSXLEN less than SXLEN
  return UNDEFINED_LEGAL_DETERMINISTIC;
} else if ((csr_value.VSXL & 0b10) != 0) {
  # MSB of VSXL represents XLEN > 64, which isn't legal
  return UNDEFINED_LEGAL_DETERMINISTIC;
} else {
  return csr_value.VSXL;
}

VTSR = csr_value.VTSR
VTW = csr_value.VTW
VTVM = csr_value.VTVM
VGEIN = if (csr_value.VGEIN <= NUM_EXTERNAL_GUEST_INTERRUPTS) {
  return csr_value.VGEIN;
} else {
  return ILLEGAL_WLRL;
}

HU = csr_value.HU
SPVP = csr_value.SPVP
SPV = csr_value.SPV
GVA = csr_value.GVA
VSBE = csr_value.VSBE