srlw

Shift right logical word

This instruction is defined by:

  • I, version >= I@2.1.0

This instruction is included in the following profiles:

  • MockProfile 64-bit S-mode (Mandatory)

  • MockProfile 64-bit Unpriv (Mandatory)

  • RVA20S64 (Mandatory)

  • RVA20U64 (Mandatory)

  • RVA22S64 (Mandatory)

  • RVA22U64 (Mandatory)

  • RVA23M64 (Mandatory)

  • RVA23S64 (Mandatory)

  • RVA23U64 (Mandatory)

  • RVB23M64 (Mandatory)

  • RVB23S64 (Mandatory)

  • RVB23U64 (Mandatory)

  • RVI20U32 (Mandatory)

  • RVI20U64 (Mandatory)

Encoding

svg

Assembly format

srlw rd, rs1, rs2

Synopsis

This instruction must have data-independent timing when extension Zkt is enabled.

Logical shift the 32-bit value in xs1 right by the value in the lower 5 bits of xs2, and store the sign-extended result in xd.

Access

M HS U VS VU

Always

Always

Always

Always

Always

Decode Variables

Bits<5> xs2 = $encoding[24:20];
Bits<5> xs1 = $encoding[19:15];
Bits<5> xd = $encoding[11:7];

Execution

  • IDL

  • Sail

X[xd] = %%LINK%func;sext;sext%%(X[xs1][31:0] >> X[xs2][4:0], 31);
{
  let xs1_val = (X(xs1))[31..0];
  let xs2_val = (X(xs2))[31..0];
  let result : bits(32) = match op {
    RISCV_ADDW => xs1_val + xs2_val,
    RISCV_SUBW => xs1_val - xs2_val,
    RISCV_SLLW => xs1_val << (xs2_val[4..0]),
    RISCV_SRLW => xs1_val >> (xs2_val[4..0]),
    RISCV_SRAW => shift_right_arith32(xs1_val, xs2_val[4..0])
  };
  X(xd) = sign_extend(result);
  RETIRE_SUCCESS
}