aes64ds

AES decrypt final round

Uses the two 64-bit source registers to represent the entire AES state, and produces half of the next round output, applying the Inverse ShiftRows and SubBytes steps.

This instruction must have data-independent timing when extension Zkt is enabled.

Assembly format

aes64ds rd, rs1, rs2

Decode Variables

Bits<5> xs2 = $encoding[24:20];
Bits<5> xs1 = $encoding[19:15];
Bits<5> xd = $encoding[11:7];

Execution

  • IDL

Encoding

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Defining extension

Zknd, version >= Zknd@1.0.0

Access

M

Always

Containing profiles

  • Mandatory:

  • Optional: RVA22S64, RVA22U64, RVA23M64, RVA23S64, RVB23M64, RVB23S64, RVB23U64