mcause

Machine Cause

Reports the cause of the latest exception.

Attributes

Requirement

Sm

Defining extensions

Sm

Machine mode

CSR Address

0x342

Length

* 32 when CSR[misa].MXL == 0 * 64 when CSR[misa].MXL == 1

Privilege Mode

M

Format

This CSR format changes dynamically.

mcause Format when CSR[misa].MXL == 0
Figure 1. mcause Format when CSR[misa].MXL == 0
mcause Format when CSR[misa].MXL == 1
Figure 2. mcause Format when CSR[misa].MXL == 1

Field Summary

Name Location Type Reset Value

mcause.INT

* 31 when CSR[misa].MXL == 0 * 63 when CSR[misa].MXL == 1

RW-RH

0

mcause.CODE

* 30:0 when CSR[misa].MXL == 0 * 62:0 when CSR[misa].MXL == 1

RW-RH

0

Fields

INT

Location

  • 31 when CSR[misa].MXL == 0

  • 63 when CSR[misa].MXL == 1

Description

Written by hardware when a trap is taken into M-mode.

When set, the last exception was caused by an asynchronous Interrupt.

mcause.INT is writable.

If mcause is written with an undefined cause (combination of mcause.INT and mcause.CODE), an Illegal Instruction exception occurs.

If mcause is written with an undefined cause (combination of mcause.INT and mcause.CODE), neither mcause.INT nor mcause.CODE are modified.

Type

RW-RH

Reset value

0

CODE

Location

  • 30:0 when CSR[misa].MXL == 0

  • 62:0 when CSR[misa].MXL == 1

Description

Written by hardware when a trap is taken into M-mode.

Holds the interrupt or exception code for the last taken trap.

mcause.CODE is writable.

If mcause is written with an undefined cause (combination of mcause.INT and mcause.CODE), an Illegal Instruction exception occurs.

If mcause is written with an undefined cause (combination of mcause.INT and mcause.CODE), neither mcause.INT nor mcause.CODE are modified.

Valid interrupt codes are:

<%- implemented_interrupt_codes.sort_by{ |code| code.num }.each do |code| -%>

<%= code.num %>

<%= code.name %> <%- end -%>

Valid exception codes are:

<%- implemented_exception_codes.sort_by{ |code| code.num }.each do |code| -%>

<%= code.num %>

<%= code.name %> <%- end -%>
Type

RW-RH

Reset value

0

Software write

This CSR may store a value that is different from what software attempts to write.

When a software write occurs (e.g., through csrrw), the following determines the written value:

INT = # the write only holds if the INT/CODE combination is valid
if (csr_value.INT == 1) {
  if (valid_interrupt_code?(csr_value.CODE)) {
    return 1;
  }
  return ILLEGAL_WLRL;
} else {
  if (valid_exception_code?(csr_value.CODE)) {
    return 1;
  }
  return ILLEGAL_WLRL;
}

CODE = # the write only holds if the INT/CODE combination is valid
if (csr_value.INT == 1) {
  if (valid_interrupt_code?(csr_value.CODE)) {
    return csr_value.CODE;
  }
  return ILLEGAL_WLRL;
} else {
  if (valid_exception_code?(csr_value.CODE)) {
    return csr_value.CODE;
  }
  return ILLEGAL_WLRL;
}