sltiu
Set on less than immediate unsigned
This instruction is defined by:
-
I, version >= I@2.1.0
This instruction is included in the following profiles:
-
MockProfile 64-bit S-mode (Mandatory)
-
MockProfile 64-bit Unpriv (Mandatory)
-
RVA20S64 (Mandatory)
-
RVA20U64 (Mandatory)
-
RVA22S64 (Mandatory)
-
RVA22U64 (Mandatory)
-
RVA23S64 (Mandatory)
-
RVA23U64 (Mandatory)
-
RVB23S64 (Mandatory)
-
RVB23U64 (Mandatory)
-
RVI20U32 (Mandatory)
-
RVI20U64 (Mandatory)
Synopsis
This instruction must have data-independent timing when extension Zkt is enabled. |
Places the value 1 in register xd
if register xs1
is less than the sign-extended immediate
when both are treated as unsigned numbers (i.e., the immediate is first sign-extended to
XLEN bits then treated as an unsigned number), else 0 is written to xd
.
sltiu xd, xs1, 1 sets xd to 1 if xs1 equals zero, otherwise sets xd to 0
(assembler pseudoinstruction SEQZ xd, rs ).
|
Decode Variables
Bits<12> imm = $encoding[31:20];
Bits<5> xs1 = $encoding[19:15];
Bits<5> xd = $encoding[11:7];
Execution
-
IDL
-
Sail
Bits<XLEN> sign_extend_imm = $signed(imm);
X[xd] = (X[xs1] < sign_extend_imm) ? 1 : 0;
{
let xs1_val = X(xs1);
let immext : xlenbits = sign_extend(imm);
let result : xlenbits = match op {
RISCV_ADDI => xs1_val + immext,
RISCV_SLTI => zero_extend(bool_to_bits(xs1_val <_s immext)),
RISCV_SLTIU => zero_extend(bool_to_bits(xs1_val <_u immext)),
RISCV_ANDI => xs1_val & immext,
RISCV_ORI => xs1_val | immext,
RISCV_XORI => xs1_val ^ immext
};
X(xd) = result;
RETIRE_SUCCESS
}