pmpcfg6

PMP Configuration Register 6

PMP entry configuration

Attributes

Defining Extension

Smpmp, version >= Smpmp@1.11.0

CSR Address

0x3a6

Length

* 32 when CSR[misa].MXL == 0 * 64 when CSR[misa].MXL == 1

Privilege Mode

M

Format

This CSR format changes dynamically.

pmpcfg6 Format when CSR[misa].MXL == 0
Figure 1. pmpcfg6 Format when CSR[misa].MXL == 0
pmpcfg6 Format when CSR[misa].MXL == 1
Figure 2. pmpcfg6 Format when CSR[misa].MXL == 1

Field Summary

Name Location Type Reset Value

pmpcfg6.pmp24cfg

7:0

[when,"(NUM_PMP_ENTRIES > 24)"] RW-R [when,"(NUM_PMP_ENTRIES ⇐ 24)"] RO

0

pmpcfg6.pmp25cfg

15:8

[when,"(NUM_PMP_ENTRIES > 25)"] RW-R [when,"(NUM_PMP_ENTRIES ⇐ 25)"] RO

0

pmpcfg6.pmp26cfg

23:16

[when,"(NUM_PMP_ENTRIES > 26)"] RW-R [when,"(NUM_PMP_ENTRIES ⇐ 26)"] RO

0

pmpcfg6.pmp27cfg

31:24

[when,"(NUM_PMP_ENTRIES > 27)"] RW-R [when,"(NUM_PMP_ENTRIES ⇐ 27)"] RO

0

pmpcfg6.pmp28cfg

39:32

[when,"(NUM_PMP_ENTRIES > 28)"] RW-R [when,"(NUM_PMP_ENTRIES ⇐ 28)"] RO

0

pmpcfg6.pmp29cfg

47:40

[when,"(NUM_PMP_ENTRIES > 29)"] RW-R [when,"(NUM_PMP_ENTRIES ⇐ 29)"] RO

0

pmpcfg6.pmp30cfg

55:48

[when,"(NUM_PMP_ENTRIES > 30)"] RW-R [when,"(NUM_PMP_ENTRIES ⇐ 30)"] RO

0

pmpcfg6.pmp31cfg

63:56

[when,"(NUM_PMP_ENTRIES > 31)"] RW-R [when,"(NUM_PMP_ENTRIES ⇐ 31)"] RO

0

Fields

pmp24cfg

Location

7:0

Description

PMP configuration for entry 24

The bits are as follows:

Name Location Description

L

7

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

6:5

Reserved Writes shall be ignored.

A

4:3

Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NA4* (2) - Naturally aligned four-byte region
* *NAPOT* (3) - Naturally aligned power of two
[when="PMP_GRANULARITY >= 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NAPOT* (3) - Naturally aligned power of two

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

X

2

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

1

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

0

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RW-R

RO

Reset value

0

pmp25cfg

Location

15:8

Description

PMP configuration for entry 25

The bits are as follows:

Name Location Description

L

15

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

14:13

Reserved Writes shall be ignored.

A

12:11

Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NA4* (2) - Naturally aligned four-byte region
* *NAPOT* (3) - Naturally aligned power of two
[when="PMP_GRANULARITY >= 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NAPOT* (3) - Naturally aligned power of two

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

X

10

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

9

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

8

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RW-R

RO

Reset value

0

pmp26cfg

Location

23:16

Description

PMP configuration for entry 26

The bits are as follows:

Name Location Description

L

23

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

22:21

Reserved Writes shall be ignored.

A

20:19

Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NA4* (2) - Naturally aligned four-byte region
* *NAPOT* (3) - Naturally aligned power of two
[when="PMP_GRANULARITY >= 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NAPOT* (3) - Naturally aligned power of two

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

X

18

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

17

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

16

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RW-R

RO

Reset value

0

pmp27cfg

Location

31:24

Description

PMP configuration for entry 27

The bits are as follows:

Name Location Description

L

31

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

30:29

Reserved Writes shall be ignored.

A

28:27

Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NA4* (2) - Naturally aligned four-byte region
* *NAPOT* (3) - Naturally aligned power of two
[when="PMP_GRANULARITY >= 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NAPOT* (3) - Naturally aligned power of two

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

X

26

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

25

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

24

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RW-R

RO

Reset value

0

pmp28cfg

Location

39:32

Description

PMP configuration for entry 28

The bits are as follows:

Name Location Description

L

39

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

38:37

Reserved Writes shall be ignored.

A

36:35

Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NA4* (2) - Naturally aligned four-byte region
* *NAPOT* (3) - Naturally aligned power of two
[when="PMP_GRANULARITY >= 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NAPOT* (3) - Naturally aligned power of two

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

X

34

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

33

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

32

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RW-R

RO

Reset value

0

pmp29cfg

Location

47:40

Description

PMP configuration for entry 29

The bits are as follows:

Name Location Description

L

47

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

46:45

Reserved Writes shall be ignored.

A

44:43

Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NA4* (2) - Naturally aligned four-byte region
* *NAPOT* (3) - Naturally aligned power of two
[when="PMP_GRANULARITY >= 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NAPOT* (3) - Naturally aligned power of two

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

X

42

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

41

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

40

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RW-R

RO

Reset value

0

pmp30cfg

Location

55:48

Description

PMP configuration for entry 30

The bits are as follows:

Name Location Description

L

55

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

54:53

Reserved Writes shall be ignored.

A

52:51

Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NA4* (2) - Naturally aligned four-byte region
* *NAPOT* (3) - Naturally aligned power of two
[when="PMP_GRANULARITY >= 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NAPOT* (3) - Naturally aligned power of two

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

X

50

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

49

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

48

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RW-R

RO

Reset value

0

pmp31cfg

Location

63:56

Description

PMP configuration for entry 31

The bits are as follows:

Name Location Description

L

63

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

62:61

Reserved Writes shall be ignored.

A

60:59

Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NA4* (2) - Naturally aligned four-byte region
* *NAPOT* (3) - Naturally aligned power of two
[when="PMP_GRANULARITY >= 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NAPOT* (3) - Naturally aligned power of two

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

X

58

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

57

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

56

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type

RW-R

RO

Reset value

0

Software write

This CSR may store a value that is different from what software attempts to write.

When a software write occurs (e.g., through csrrw), the following determines the written value:

pmp24cfg = if ((CSR[pmpcfg6].pmp24cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp24cfg & 0x1) == 0) && ((csr_value.pmp24cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp24cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp24cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg6].pmp24cfg;

pmp25cfg = if ((CSR[pmpcfg6].pmp25cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp25cfg & 0x1) == 0) && ((csr_value.pmp25cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp25cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp25cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg6].pmp25cfg;

pmp26cfg = if ((CSR[pmpcfg6].pmp26cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp26cfg & 0x1) == 0) && ((csr_value.pmp26cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp26cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp26cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg6].pmp26cfg;

pmp27cfg = if ((CSR[pmpcfg6].pmp27cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp27cfg & 0x1) == 0) && ((csr_value.pmp27cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp27cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp27cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg6].pmp27cfg;

pmp28cfg = if ((CSR[pmpcfg6].pmp28cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp28cfg & 0x1) == 0) && ((csr_value.pmp28cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp28cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp28cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg6].pmp28cfg;

pmp29cfg = if ((xlen() == 64) && (CSR[pmpcfg6].pmp29cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp29cfg & 0x1) == 0) && ((csr_value.pmp29cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp29cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp29cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg6].pmp29cfg;

pmp30cfg = if ((xlen() == 64) && (CSR[pmpcfg6].pmp30cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp30cfg & 0x1) == 0) && ((csr_value.pmp30cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp30cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp30cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg6].pmp30cfg;

pmp31cfg = if ((xlen() == 64) && (CSR[pmpcfg6].pmp31cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp31cfg & 0x1) == 0) && ((csr_value.pmp31cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp31cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp31cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg6].pmp31cfg;