scontext

Supervisor Context

This optional register is only accessible in S/HS-mode, VS-mode, M-mode and Debug Mode. Accessibility of this CSR is controlled by mstateen0[57] and hstateen0[57] in the Smstateen extension. Enabling scontext can be a security risk in a virtualized system with a hypervisor that does not swap scontext.

Attributes

Defining Extension

allOf: * Sdtrig, version >= Sdtrig@1.0.0 * S, version >= S@1.11.0

CSR Address

0x5a8

Length

* 32 when (priv_mode() == PrivilegeMode::M && CSR[misa].MXL == 0)

(priv_mode() == PrivilegeMode::S && CSR[mstatus].SXL == %%)

(priv_mode() == PrivilegeMode::VS && CSR[hstatus].VSXL == %%) * 64 when (priv_mode() == PrivilegeMode::M && CSR[misa].MXL == 1)

(priv_mode() == PrivilegeMode::S && CSR[mstatus].SXL == %%)

(priv_mode() == PrivilegeMode::VS && CSR[hstatus].VSXL == %%)

Privilege Mode

S

Format

This CSR format changes dynamically.

scontext Format when (priv_mode() == PrivilegeMode::M && CSR[misa].MXL == 0) || (priv_mode() == PrivilegeMode::S && CSR[mstatus].SXL == 0) || (priv_mode() == PrivilegeMode::VS && CSR[hstatus].VSXL == 0)
Figure 1. scontext Format when (priv_mode() == PrivilegeMode::M && CSR[misa].MXL == 0) || (priv_mode() == PrivilegeMode::S && CSR[mstatus].SXL == 0) || (priv_mode() == PrivilegeMode::VS && CSR[hstatus].VSXL == 0)
scontext Format when (priv_mode() == PrivilegeMode::M && CSR[misa].MXL == 1) || (priv_mode() == PrivilegeMode::S && CSR[mstatus].SXL == 1) || (priv_mode() == PrivilegeMode::VS && CSR[hstatus].VSXL == 1)
Figure 2. scontext Format when (priv_mode() == PrivilegeMode::M && CSR[misa].MXL == 1) || (priv_mode() == PrivilegeMode::S && CSR[mstatus].SXL == 1) || (priv_mode() == PrivilegeMode::VS && CSR[hstatus].VSXL == 1)

Field Summary

Name Location Type Reset Value

scontext.DATA

31:0

RW

0

Fields

DATA

Location

31:0

Description

Supervisor mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context.

An implementation may tie any number of high bits in this field to 0. It’s recommended to implement 16 bits on RV32 and 32 bits on RV64.

Type

RW

Reset value

0

Software write

This CSR may store a value that is different from what software attempts to write.

When a software write occurs (e.g., through csrrw), the following determines the written value:

DATA = # check if mstateen0 or hstateen0 is clear
if (implemented?(ExtensionName::Smstateen) && ((CSR[mstateen0].CONTEXT != 0) || (CSR[hstateen0].CONTEXT != 0))) {
  unimplemented_csr($encoding);
}

# enforce width of SCONTEXT
Bits<32> scontext_value = csr_value.DATA & ((32'1 << DBG_SCONTEXT_WIDTH) - 1);
return scontext_value;

Software read

This CSR may return a value that is different from what is stored in hardware.

if (implemented?(ExtensionName::Smstateen) && mstateen0.CONTEXT != 0) || (hstateen0.CONTEXT != 0) {
  unimplemented_csr($encoding);
}