hstateen0h

Upper 32 bits of Hypervisor State Enable 0 Register

For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State Enable 0), mstateen1, mstateen2, and mstateen3. If supervisor mode is implemented, another four CSRs are defined at supervisor level: sstateen0, sstateen1, sstateen2, and sstateen3. And if the hypervisor extension is implemented, another set of CSRs is added: hstateen0, hstateen1, hstateen2, and hstateen3.

For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding set of high-half CSRs for the upper 32 bits of each register: mstateen0h, mstateen1h, mstateen2h, mstateen3h, hstateen0h, hstateen1h, hstateen2h, and hstateen3h.

Attributes

Defining Extension

  • allOf:

    • H, version >= H@1.0.0

    • Smstateen, version >= Smstateen@1.0.0

    • Ssstateen, version >= Ssstateen@1.0.0

CSR Address

0x61c

Length

32-bit

Privilege Mode

S

Format

hstateen0h format
Figure 1. hstateen0h format

Field Summary

Name Location Type Reset Value

hstateen0h.SE0

31

RW

UNDEFINED_LEGAL

hstateen0h.ENVCFG

30

RW

UNDEFINED_LEGAL

hstateen0h.CSRIND

28

RW

UNDEFINED_LEGAL

hstateen0h.AIA

27

RW

UNDEFINED_LEGAL

hstateen0h.IMSIC

26

RW

UNDEFINED_LEGAL

hstateen0h.CONTEXT

25

RW

UNDEFINED_LEGAL

hstateen0h.CTR

22

RW

0

Fields

SE0

Location

31

Description

The SE0 bit in hstateen0h controls access to the sstateen0 CSR.

Type

RW

Reset value

UNDEFINED_LEGAL

ENVCFG

Location

30

Description

The ENVCFG bit in hstateen0h controls access to the senvcfg CSRs.

Type

RW

Reset value

UNDEFINED_LEGAL

CSRIND

Location

28

Description

The CSRIND bit in hstateen0h controls access to the siselect and the sireg*, (really vsiselect and vsireg*) CSRs provided by the Sscsrind extensions.

Type

RW

Reset value

UNDEFINED_LEGAL

AIA

Location

27

Description

The AIA bit in hstateen0h controls access to all state introduced by the Ssaia extension and is not controlled by either the CSRIND or the IMSIC bits of hstateen0.

Type

RW

Reset value

UNDEFINED_LEGAL

IMSIC

Location

26

Description

The IMSIC bit in hstateen0h controls access to the guest IMSIC state, including CSRs stopei (really vstopei), provided by the Ssaia extension.

Setting the IMSIC bit in hstateen0h to zero prevents a virtual machine from accessing the hart’s IMSIC the same as setting hstatusVGEIN = 0.

Type

RW

Reset value

UNDEFINED_LEGAL

CONTEXT

Location

25

Description

The CONTEXT bit in hstateen0h controls access to the scontext CSR provided by the Sdtrig extension.

Type

RW

Reset value

UNDEFINED_LEGAL

CTR

Location

22

Description

If the H extension is implemented and mstateen0.CTR=1, the hstateen0.CTR bit controls access to supervisor CTR state when V=1. This state includes sctrctl (really vsctrctl), sctrstatus, and sireg* (really vsireg*) when siselect (really vsiselect) is in 0x200..0x2FF. hstateen0.CTR is read-only 0 when mstateen0.CTR=0.

Type

RW

Reset value

0

Software write

This CSR may store a value that is different from what software attempts to write.

When a software write occurs (e.g., through csrrw), the following determines the written value:

SE0 = if (CSR[mstateen0].SE0 == 1'b0){
  return 0;
}
CSR[hstateen0].SE0 = csr_value.SE0;
return csr_value.SE0;

ENVCFG = if (CSR[mstateen0].ENVCFG == 1'b0){
  return 0;
}
CSR[hstateen0].ENVCFG = csr_value.ENVCFG;
return csr_value.ENVCFG;

CSRIND = if (CSR[mstateen0].CSRIND == 1'b0){
  return 0;
}
CSR[hstateen0].CSRIND = csr_value.CSRIND;
return csr_value.CSRIND;

AIA = if (CSR[mstateen0].AIA == 1'b0){
  return 0;
}
CSR[hstateen0].AIA = csr_value.AIA;
return csr_value.AIA;

IMSIC = if (CSR[mstateen0].IMSIC == 1'b0){
  return 0;
}
CSR[hstateen0].IMSIC = csr_value.IMSIC;
return csr_value.IMSIC;

CONTEXT = if (CSR[mstateen0].CONTEXT == 1'b0){
  return 0;
}
CSR[hstateen0].CONTEXT = csr_value.CONTEXT;
return csr_value.CONTEXT;

CTR = if (CSR[mstateen0].CTR == 1'b0){
  return 0;
}
CSR[hstateen0].CTR = csr_value.CTR;
return csr_value.CTR;

Software read

This CSR may return a value that is different from what is stored in hardware.

return $bits(hstateen0)[63:32];