fflags
Floating-Point Accrued Exceptions
The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction since the field was last reset by software.
The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.
As allowed by the standard, we do not support traps on floating-point exceptions in the F extension, but instead require explicit checks of the flags in software. We considered adding branches controlled directly by the contents of the floating-point accrued exception flags, but ultimately chose to omit these instructions to keep the ISA simple.
Attributes
Requirement |
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|---|---|---|---|
Defining extensions |
|
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CSR Address |
0x1 |
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Length |
32-bit |
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Privilege Mode |
U |
Fields
NV
- Location
-
4
- Description
-
Set by hardware when a floating point operation is invalid and stays set until explicitly cleared by software.
- Type
-
RW-H
- Reset value
-
UNDEFINED_LEGAL
DZ
- Location
-
3
- Description
-
Set by hardware when a floating point divide attempts to divide by zero and stays set until explicitly cleared by software.
- Type
-
RW-H
- Reset value
-
UNDEFINED_LEGAL
OF
- Location
-
2
- Description
-
Set by hardware when a floating point operation overflows and stays set until explicitly cleared by software.
- Type
-
RW-H
- Reset value
-
UNDEFINED_LEGAL
Software write
This CSR may store a value that is different from what software attempts to write.
When a software write occurs (e.g., through csrrw), the following determines the written value:
NV = CSR[fcsr].NV = csr_value.NV;
return csr_value.NV;
DZ = CSR[fcsr].DZ = csr_value.DZ;
return csr_value.DZ;
OF = CSR[fcsr].OF = csr_value.OF;
return csr_value.OF;
UF = CSR[fcsr].UF = csr_value.UF;
return csr_value.UF;
NX = CSR[fcsr].NX = csr_value.NX;
return csr_value.NX;