hstateen2h

Upper 32 bits of Hypervisor State Enable 2 Register

For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State Enable 0), mstateen1, mstateen2, and mstateen3. If supervisor mode is implemented, another four CSRs are defined at supervisor level: sstateen0, sstateen1, sstateen2, and sstateen3. And if the hypervisor extension is implemented, another set of CSRs is added: hstateen0, hstateen1, hstateen2, and hstateen3.

For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding set of high-half CSRs for the upper 32 bits of each register: mstateen0h, mstateen1h, mstateen2h, mstateen3h, hstateen0h, hstateen1h, hstateen2h, and hstateen3h.

Attributes

Defining Extension

  • allOf:

    • H, version >= H@1.0.0

    • Smstateen, version >= Smstateen@1.0.0

    • Ssstateen, version >= Ssstateen@1.0.0

CSR Address

0x61e

Length

32-bit

Privilege Mode

S

Format

hstateen2h format
Figure 1. hstateen2h format

Field Summary

Name Location Type Reset Value

hstateen2h.SE0

31

RW

UNDEFINED_LEGAL

Fields

SE0

Location

31

Description

The SE0 bit in hstateen2h controls access to the sstateen2 CSR.

Type

RW

Reset value

UNDEFINED_LEGAL

Software write

This CSR may store a value that is different from what software attempts to write.

When a software write occurs (e.g., through csrrw), the following determines the written value:

SE0 = if (CSR[mstateen2].SE0 == 1'b0){
  return 0;
}
CSR[hstateen2].SE0 = csr_value.SE0;
return csr_value.SE0;

Software read

This CSR may return a value that is different from what is stored in hardware.

return $bits(hstateen2)[63:32];