fsd

Floating-Point Store Double-Precision

The fsd instruction stores a double-precision value from the floating-point registers to memory. It is guaranteed to execute atomically if the effective address is naturally aligned and XLEN≥64. It doesn’t modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.

Assembly format

fsd fs2, imm(rs1)

Decode Variables

Bits<12> imm = {$encoding[31:25], $encoding[11:7]};
Bits<5> fs2 = $encoding[24:20];
Bits<5> xs1 = $encoding[19:15];

Execution

  • IDL

Encoding

svg

Defining extension

D, version >= D@2.2.0

Access

M

Always

Containing profiles

  • Mandatory: RVA20S64, RVA20U64, RVA22S64, RVA22U64, RVA23M64, RVA23S64, RVA23U64, RVB23M64, RVB23S64, RVB23U64

  • Optional: RVI20U32, RVI20U64