miselect

Machine Indirect Register Select

The CSRs listed in the table above provide a window for accessing register state indirectly. The value of miselect determines which register is accessed upon read or write of each of the machine indirect alias CSRs (mireg*). miselect value ranges are allocated to dependent extensions, which specify the register state accessible via each miregi register, for each miselect value. miselect is a WARL register.

The miselect register implements at least enough bits to support all implemented miselect values (corresponding to the implemented extensions that utilize miselect/mireg* to indirectly access register state). The miselect register may be read-only zero if there are no extensions implemented that utilize it.

Values of miselect with the most-significant bit set (bit XLEN - 1 = 1) are designated only for custom use, presumably for accessing custom registers through the alias CSRs. Values of miselect with the most-significant bit clear are designated only for standard use and are reserved until allocated to a standard architecture extension.

If XLEN is changed, the most-significant bit of miselect moves to the new position, retaining its value from before.

An implementation is not required to support any custom values for miselect.

Attributes

Defining Extension

Smcsrind, version >= Smcsrind@1.0.0

CSR Address

0x350

Length

* 32 when CSR[misa].MXL == 0 * 64 when CSR[misa].MXL == 1

Privilege Mode

M

Format

This CSR format changes dynamically.

miselect Format when CSR[misa].MXL == 0
Figure 1. miselect Format when CSR[misa].MXL == 0
miselect Format when CSR[misa].MXL == 1
Figure 2. miselect Format when CSR[misa].MXL == 1

Field Summary

Name Location Type Reset Value

miselect.VALUE

* 31:0 when CSR[misa].MXL == 0 * 63:0 when CSR[misa].MXL == 1

RW

UNDEFINED_LEGAL

Fields

VALUE

Location
  • 31:0 when CSR[misa].MXL == 0

  • 63:0 when CSR[misa].MXL == 1

Description

Selects which indirect register is accessed via mireg*.

Type

RW

Reset value

UNDEFINED_LEGAL