senvcfg

Supervisor Environment Configuration

Contains fields that control certain characteristics of the U-mode execution environment.

Attributes

Defining Extension

allOf: * S, version >=1.12

  • U, version >= U@1.0.0

CSR Address

0x10a

Length

64-bit

Privilege Mode

S

Format

senvcfg format
Figure 1. senvcfg format

Field Summary

Name Location Type Reset Value

senvcfg.CBZE

7

RW

UNDEFINED_LEGAL

senvcfg.CBCFE

6

RW

UNDEFINED_LEGAL

senvcfg.CBIE

5:4

RW-R

UNDEFINED_LEGAL

senvcfg.FIOM

0

RW

0

Fields

CBZE

Location

7

Description

Cache Block Zero instruction Enable

Bit is read-only 0 when menvcfg.CBZE is clear.

Enables the execution of the cache block zero instruction, cbo.zero, in U-mode<% if ext?(:H) %> and (in conjunction with henvcfg.CBZE) VU-mode<% end %>.

  • 0: The instruction raises an illegal instruction<% if ext?(:H) %> or virtual instruction exception<% end %>

  • 1: The instruction is executed

To summarize access:

menvcfg.CBZE senvcfg.CBZE behavior

0

read-only 0

1

writable, independent bit from menvcfg.CBZE

See cbo.zero for a summary of the effect.

Type

RW

Reset value

UNDEFINED_LEGAL

CBCFE

Location

6

Description

Cache Block Clean and Flush instruction Enable

Enables the execution of the cache block clean instruction, cbo.clean, and the cache block flush instruction, cbo.flush, <% if ext?(:S) %> in S-mode <% elsif ext?(:U) %> in U-mode <% end %>.

  • 0: The instruction raises an illegal instruction <% if ext?(:H) %>or virtual instruction exception<% end %>

  • 1: The instruction is executed

To summarize access:

menvcfg.CBCFE senvcfg.CBCFE behavior

0

read-only 0

1

writable, independent bit from menvcfg.CBCFE

See cbo.clean and/or cbo.flush for a summary of the effect.

Type

RW

Reset value

UNDEFINED_LEGAL

CBIE

Location

5:4

Description

Cache Block Invalidate instruction Enable

This field has restricted values based on the value of menvcfg.CBIE. When an invalid value is written, it is ignored and the field remains unchanged.

menvcfg.CBIE Valid values of senvcfg.CBIE

00

00

01

00, 01

11

00, 01, 11

Controls execution of the cache block invalidate instruction, cbo.inval, in U-mode <% if ext?(:H) %> and VU-mode (together with henvcfg.CBIE) <% end %> .

  • 00: The instruction raises an illegal instruction or virtual instruction exception

  • 01: The instruction is executed and performs a flush operation

  • 10: Reserved

  • 11: The instruction is executed and performs an invalidate operation

See cbo.inval for more details.

Type

RW-R

Reset value

UNDEFINED_LEGAL

FIOM

Location

0

Description

Fence of I/O implies Memory

When either senvcfg.FIOM or menvcfg.FIOM is set, FENCE instructions ordering I/O regions also implicitly order memory regions when executed in U-mode as follows:

Instruction bit Meaning when set

PI
PO

Predecessor device input and memory reads (PR implied)
Predecessor device output and memory writes (PW implied)

SI
SO

Successor device input and memory reads (SR implied)
Successor device output and memory writes (SW implied)

Similarly, in U-mode when FIOM=1, if an atomic instruction that accesses a region ordered as device I/O has its aq and/or rl bit set, then that instruction is ordered as though it accesses both device I/O and memory.

See fence for more details.

Type

RW

Reset value

0

Software write

This CSR may store a value that is different from what software attempts to write.

When a software write occurs (e.g., through csrrw), the following determines the written value:

CBZE = csr_value.CBZE
CBCFE = csr_value.CBCFE
CBIE = if (csr_value.CBIE == 0 || csr_value.CBIE == 1 || csr_value.CBIE == 3) {
  return csr_value.CBIE;
} else {
  return UNDEFINED_LEGAL_DETERMINISTIC;
}

FIOM = csr_value.FIOM