vsepc

Virtual Supervisor Exception Program Counter

Written with the PC of an instruction on an exception or interrupt taken in VS-mode.

Also controls where the hart jumps on an exception return from VS-mode.

Attributes

Requirement

H

Defining extensions

H

Hypervisor

CSR Address

0x241

Virtual CSR Address

0x141

Length

64-bit

Privilege Mode

VS

Format

vsepc format
Figure 1. vsepc format

Field Summary

Name Location Type Reset Value

vsepc.PC

63:0

RW-RH

UNDEFINED_LEGAL

Fields

PC

Location

63:0

Description

When a trap is taken into VS-mode, vsepc.PC is written with the virtual address of the instruction that was interrupted or that encountered the exception. Otherwise, vsepc.PC is never written by the implementation, though it may be explicitly written by software.

On an exception return from VS-mode (from the SRET instruction), control transfers to the virtual address read out of vsepc.PC.

Because PCs are always <% if ext?(:C) %>halfword<% else %>word<% end %>-aligned, <% if ext?(:C) %>bit 0<% else %>bits 1:0<% end %> of vsepc.PC are always read-only 0.

When misa.C is clear, bit 1 is masked to zero. Writes to bit 1 are still captured, and may be visible on the next read with misa.C is set.

Holds bits 63:<%= ext?(:C) ? 2 : 1 %> of the virtual address associated with an exception.

Type

RW-RH

Reset value

UNDEFINED_LEGAL

Software write

This CSR may store a value that is different from what software attempts to write.

When a software write occurs (e.g., through csrrw), the following determines the written value:

PC = return csr_value.PC & ~64'b1;

Software read

This CSR may return a value that is different from what is stored in hardware.

if (implemented?(ExtensionName::C) && CSR[misa].C == 1'b1) {
  return CSR[sepc].PC & ~64'b1;
} else {
  return CSR[sepc].PC;
}