addiw

Add immediate word

Add an immediate to the 32-bit value in xs1, and store the sign extended result in xd

This instruction must have data-independent timing when extension Zkt is enabled.

Assembly format

addiw rd, rs1, imm

Decode Variables

Bits<12> imm = $encoding[31:20];
Bits<5> xs1 = $encoding[19:15];
Bits<5> xd = $encoding[11:7];

Execution

  • IDL

  • Sail

XReg operand = sext(X[xs1], 31);
X[xd] = sext(operand + imm, 31);
{
  let result : xlenbits = sign_extend(imm) + X(xs1);
  X(xd) = sign_extend(result[31..0]);
  RETIRE_SUCCESS
}

Encoding

svg

Defining extension

  • I, version >= I@2.1.0

Access

M HS U VS VU

Always

Always

Always

Always

Always

Containing profiles

  • Mandatory: MockProfile 64-bit S-mode, MockProfile 64-bit Unpriv, RVA20S64, RVA20U64, RVA22S64, RVA22U64, RVA23M64, RVA23S64, RVA23U64, RVB23M64, RVB23S64, RVB23U64, RVI20U32, RVI20U64

  • Optional: