mhpmevent10

Machine Hardware Performance Counter 10 Control

Programmable hardware performance counter event selector <% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>

Attributes

Requirement

Smhpm

Defining extensions

Smhpm

M-mode programmable hardware performance counters

CSR Address

0x32a

Length

64-bit

Privilege Mode

M

Format

mhpmevent10 format
Figure 1. mhpmevent10 format

Field Summary

Name Location Type Reset Value

mhpmevent10.OF

63

[when,"HPM_COUNTER_EN[10]"] RW-H [when,"!(HPM_COUNTER_EN[10])"] RO

UNDEFINED_LEGAL

mhpmevent10.MINH

62

[when,"HPM_COUNTER_EN[10]"] RW [when,"!(HPM_COUNTER_EN[10])"] RO

UNDEFINED_LEGAL

mhpmevent10.SINH

61

[when,"HPM_COUNTER_EN[10] && implemented?(ExtensionName::S && CSR[misa].S == 1’b1)"] RW [when,"!HPM_COUNTER_EN[10] && implemented?(ExtensionName::S && CSR[misa].S == 1’b1)"] RO

UNDEFINED_LEGAL

mhpmevent10.UINH

60

[when,"HPM_COUNTER_EN[10] && implemented?(ExtensionName::U && CSR[misa].U == 1’b1)"] RW [when,"!HPM_COUNTER_EN[10] && implemented?(ExtensionName::U && CSR[misa].U == 1’b1)"] RO

UNDEFINED_LEGAL

mhpmevent10.VSINH

59

[when,"(HPM_COUNTER_EN[10]) && implemented?(ExtensionName::H && CSR[misa].H == 1’b1)"] RW [when,"!(HPM_COUNTER_EN[10]) && implemented?(ExtensionName::H && CSR[misa].H == 1’b1)"] RO

UNDEFINED_LEGAL

mhpmevent10.VUINH

58

[when,"HPM_COUNTER_EN[10] && implemented?(ExtensionName::H && CSR[misa].H == 1’b1)"] RW [when,"!HPM_COUNTER_EN[10] && implemented?(ExtensionName::H && CSR[misa].H == 1’b1)"] RO

UNDEFINED_LEGAL

mhpmevent10.EVENT

57:0

[when,"HPM_COUNTER_EN[10]"] RW [when,"!(HPM_COUNTER_EN[10])"] RO

UNDEFINED_LEGAL

Fields

OF

Location

63

Description

Overflow status and interrupt disable.

The OF bit is set when the corresponding hpmcounter overflows, and remains set until written by software. Since hpmcounter values are unsigned values, overflow is defined as unsigned overflow of the implemented counter bits.

The OF bit is sticky; it stays set until explicitly cleared by a CSR write.

A Local Counter Overflow Interrupt (LCOFI) is generated when OF is clear and mhpmcounter10 overflows.

Type

RW-H

RO

Reset value

UNDEFINED_LEGAL

MINH

Location

62

Description

When set, mhpmcounter10 does not increment while the hart in operating in M-mode.

Type

RW

RO

Reset value

UNDEFINED_LEGAL

SINH

Location

61

Description

When set, mhpmcounter10 does not increment while the hart in operating in (H)S-mode.

Type

RW

RO

Reset value

UNDEFINED_LEGAL

UINH

Location

60

Description

When set, mhpmcounter10 does not increment while the hart in operating in U-mode.

Type

RW

RO

Reset value

UNDEFINED_LEGAL

VSINH

Location

59

Description

When set, mhpmcounter10 does not increment while the hart in operating in VS-mode.

Type

RW

RO

Reset value

UNDEFINED_LEGAL

VUINH

Location

58

Description

When set, mhpmcounter10 does not increment while the hart in operating in VU-mode.

Type

RW

RO

Reset value

UNDEFINED_LEGAL

EVENT

Location

57:0

Description

Event selector for performance counter mhpmcounter10.

Type

RW

RO

Reset value

UNDEFINED_LEGAL

Software write

This CSR may store a value that is different from what software attempts to write.

When a software write occurs (e.g., through csrrw), the following determines the written value:

OF = csr_value.OF
MINH = csr_value.MINH
SINH = csr_value.SINH
UINH = csr_value.UINH
VSINH = csr_value.VSINH
VUINH = csr_value.VUINH
EVENT = if ($array_includes?(HPM_EVENTS, csr_value.EVENT)) {
  return csr_value.EVENT;
} else {
  return UNDEFINED_LEGAL_DETERMINISTIC;
}