hstateen0
Hypervisor State Enable 0 Register
Each bit of a stateen CSR controls less-privileged access to an extension’s state,
for an extension that was not deemed "worthy" of a full XS field in sstatus like the
FS and VS fields for the F and V extensions.
The number of registers provided at each level is four because it is believed that 4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for supervisor level, will be adequate for many years to come, perhaps for as long as the RISC-V ISA is in use. The exact number four is an attempted compromise between providing too few bits on the one hand and going overboard with CSRs that will never be used on the other.
The stateen registers at each level control access to state at all less-privileged
levels, but not at its own level.
When a stateen CSR prevents access to state for a privilege mode, attempting to execute
in that privilege mode an instruction that implicitly updates the state without reading
it may or may not raise an illegal instruction or virtual instruction exception.
Such cases must be disambiguated by being explicitly specified one way or the other.
In some cases, the bits of the stateen CSRs will have a dual purpose as enables for the
ISA extensions that introduce the controlled state.
With the hypervisor extension, the hstateen CSRs have identical encodings to the mstateen CSRs,
except controlling accesses for a virtual machine (from VS and VU modes).
For every bit in an hstateen CSR that is zero (whether read-only zero or set to zero),
the same bit appears as read-only zero in sstateen when accessed in VS-mode.
A bit in an hstateen CSR cannot be read-only one unless the same bit is read-only one
in the matching mstateen CSR.
Attributes
Defining Extension |
|
|---|---|
CSR Address |
0x60c |
Length |
64-bit |
Privilege Mode |
S |
Field Summary
| Name | Location | Type | Reset Value |
|---|---|---|---|
63 |
RW |
UNDEFINED_LEGAL |
|
62 |
RW |
UNDEFINED_LEGAL |
|
60 |
RW |
UNDEFINED_LEGAL |
|
59 |
RW |
UNDEFINED_LEGAL |
|
58 |
RW |
UNDEFINED_LEGAL |
|
57 |
RW |
UNDEFINED_LEGAL |
|
54 |
RW |
0 |
|
2 |
RW |
UNDEFINED_LEGAL |
|
1 |
RW |
UNDEFINED_LEGAL |
|
0 |
RW |
UNDEFINED_LEGAL |
Software write
This CSR may store a value that is different from what software attempts to write.
When a software write occurs (e.g., through csrrw), the following determines the written value:
SE0 = if (CSR[mstateen0].SE0 == 1'b0){
return 0;
}
return csr_value.SE0;
ENVCFG = if (CSR[mstateen0].ENVCFG == 1'b0){
return 0;
}
return csr_value.ENVCFG;
CSRIND = if (CSR[mstateen0].CSRIND == 1'b0){
return 0;
}
return csr_value.CSRIND;
AIA = if (CSR[mstateen0].AIA == 1'b0){
return 0;
}
return csr_value.AIA;
IMSIC = if (CSR[mstateen0].IMSIC == 1'b0){
return 0;
}
return csr_value.IMSIC;
CONTEXT = if (CSR[mstateen0].CONTEXT == 1'b0){
return 0;
}
return csr_value.CONTEXT;
CTR = if (CSR[mstateen0].CTR == 1'b0){
return 0;
}
return csr_value.CTR;
JVT = if (CSR[mstateen0].JVT == 1'b0){
return 0;
}
return csr_value.JVT;
FCSR = if (CSR[mstateen0].FCSR == 1'b0){
return 0;
}
return csr_value.FCSR;
C = if (CSR[mstateen0].C == 1'b0){
return 0;
}
return csr_value.C;