ror
Rotate right (Register)
This instruction is defined by:
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anyOf:
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B, version >= B@1.0.0
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Zbb, version >= Zbb@1.0.0
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Zbkb, version >= Zbkb@1.0.0
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Zk, version >= Zk@1.0.0
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Zkn, version >= Zkn@1.0.0
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Zks, version >= Zks@1.0.0
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This instruction is included in the following profiles:
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RVA22U64 (Mandatory)
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RVA23U64 (Mandatory)
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RVB23U64 (Mandatory)
Synopsis
| This instruction must have data-independent timing when extension Zkt is enabled. |
This instruction performs a rotate right of rs1 by the amount in least-significant log2(XLEN) bits of rs2.
Decode Variables
Bits<5> rs2 = $encoding[24:20];
Bits<5> rs1 = $encoding[19:15];
Bits<5> rd = $encoding[11:7];idl
Execution
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IDL
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Sail
if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
}
XReg shamt = (xlen() == 32) ? X[rs2][4:0] : X[rs2][5:0];
X[rd] = (X[rs1] >> shamt) | (X[rs1] << (xlen() - shamt));idl
{
let rs1_val = X(rs1);
let rs2_val = X(rs2);
let result : xlenbits = match op {
RISCV_ANDN => rs1_val & ~(rs2_val),
RISCV_ORN => rs1_val | ~(rs2_val),
RISCV_XNOR => ~(rs1_val ^ rs2_val),
RISCV_MAX => to_bits(sizeof(xlen), max(signed(rs1_val), signed(rs2_val))),
RISCV_MAXU => to_bits(sizeof(xlen), max(unsigned(rs1_val), unsigned(rs2_val))),
RISCV_MIN => to_bits(sizeof(xlen), min(signed(rs1_val), signed(rs2_val))),
RISCV_MINU => to_bits(sizeof(xlen), min(unsigned(rs1_val), unsigned(rs2_val))),
RISCV_ROL => if sizeof(xlen) == 32
then rs1_val <<< rs2_val[4..0]
else rs1_val <<< rs2_val[5..0],
RISCV_ROR => if sizeof(xlen) == 32
then rs1_val >>> rs2_val[4..0]
else rs1_val >>> rs2_val[5..0]
};
X(rd) = result;
RETIRE_SUCCESS
}sail