mcycle

Machine Cycle Counter

Counts the number of clock cycles executed by the processor core on which the hart is running. The counter has 64-bit precision on all RV32 and RV64 harts.

The mcycle CSR may be shared between harts on the same core, in which case writes to mcycle will be visible to those harts. The platform should provide a mechanism to indicate which harts share an mcycle CSR.

Attributes

Requirement

Zicntr

Defining extensions

Zicntr

Base Counters and Timers

CSR Address

0xb00

Length

64-bit

Privilege Mode

M

Format

mcycle format
Figure 1. mcycle format

Field Summary

Name Location Type Reset Value

mcycle.COUNT

63:0

RW-RH

UNDEFINED_LEGAL

Fields

COUNT

Location

63:0

Description

Cycle counter.

<%- if ext?(:Zicntr) -%> Aliased as cycle. <%- end -%>

Increments every cycle unless:

  • mcountinhibit.CY <%- if ext?(:Smcdeleg) -%>or its alias scountinhibit.CY<%- end -%> is set <%- if ext?(:Smcntrpmf) -%>

  • mcyclecfg.MINH is set and the current privilege level is M <%- if ext?(:S) -%>

  • mcyclecfg.SINH <%- if ext?(:Ssccfg) -%>or its alias instretcfg.SINH<%- end -%> is set and the current privilege level is (H)S <%- end -%> <%- if ext?(:U) -%>

  • mcyclecfg.UINH <%- if ext?(:Ssccfg) -%>or its alias instretcfg.SINH<%- end -%> is set and the current privilege level is U <%- end -%> <%- if ext?(:H) -%>

  • mcyclecfg.VSINH <%- if ext?(:Ssccfg) -%>or its alias instretcfg.SINH<%- end -%> is set and the current privilege level is VS

  • mcyclecfg.VUINH <%- if ext?(:Ssccfg) -%>or its alias instretcfg.SINH<%- end -%> is set and the current privilege level is VU <%- end -%> <%- end -%>

    Type

    RW-RH

    Reset value

    UNDEFINED_LEGAL

Software write

This CSR may store a value that is different from what software attempts to write.

When a software write occurs (e.g., through csrrw), the following determines the written value:

COUNT = # since writes to this register may not be hart-local, it must be handled
# as a special case
if (xlen() == 32) {
  return sw_write_mcycle({read_mcycle()[63:31], csr_value.COUNT[31:0]});
} else {
  return sw_write_mcycle(csr_value.COUNT);
}

Software read

This CSR may return a value that is different from what is stored in hardware.

return read_mcycle();