pmpcfg10

PMP Configuration Register 10

PMP entry configuration

Attributes

Defining Extension

  • Smpmp, version >= Smpmp@1.11.0

CSR Address

0x3aa

Length

#<ConfiguredArchitecture:0x00007f75efbd67c8>-bit

Privilege Mode

M

Format

This CSR format changes dynamically.

pmpcfg10 Format when CSR[misa].MXL == 0
Figure 1. pmpcfg10 Format when CSR[misa].MXL == 0
pmpcfg10 Format when CSR[misa].MXL == 1
Figure 2. pmpcfg10 Format when CSR[misa].MXL == 1

Field Summary

Name Location Type Reset Value

pmpcfg10.pmp40cfg

7:0

UNDEFINED_LEGAL

pmpcfg10.pmp41cfg

15:8

UNDEFINED_LEGAL

pmpcfg10.pmp42cfg

23:16

UNDEFINED_LEGAL

pmpcfg10.pmp43cfg

31:24

UNDEFINED_LEGAL

pmpcfg10.pmp44cfg

39:32

UNDEFINED_LEGAL

pmpcfg10.pmp45cfg

47:40

UNDEFINED_LEGAL

pmpcfg10.pmp46cfg

55:48

UNDEFINED_LEGAL

pmpcfg10.pmp47cfg

63:56

UNDEFINED_LEGAL

Fields

pmp40cfg

Location

7:0

Description

PMP configuration for entry 40

The bits are as follows:

Name Location Description

L

7

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

6:5

Reserved Writes shall be ignored.

A

4:3

Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NA4* (2) - Naturally aligned four-byte region
* *NAPOT* (3) - Naturally aligned power of two
[when="PMP_GRANULARITY >= 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NAPOT* (3) - Naturally aligned power of two

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

X

2

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

1

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

0

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type
Reset value

UNDEFINED_LEGAL

pmp41cfg

Location

15:8

Description

PMP configuration for entry 41

The bits are as follows:

Name Location Description

L

15

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

14:13

Reserved Writes shall be ignored.

A

12:11

Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NA4* (2) - Naturally aligned four-byte region
* *NAPOT* (3) - Naturally aligned power of two
[when="PMP_GRANULARITY >= 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NAPOT* (3) - Naturally aligned power of two

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

X

10

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

9

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

8

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type
Reset value

UNDEFINED_LEGAL

pmp42cfg

Location

23:16

Description

PMP configuration for entry 42

The bits are as follows:

Name Location Description

L

23

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

22:21

Reserved Writes shall be ignored.

A

20:19

Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NA4* (2) - Naturally aligned four-byte region
* *NAPOT* (3) - Naturally aligned power of two
[when="PMP_GRANULARITY >= 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NAPOT* (3) - Naturally aligned power of two

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

X

18

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

17

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

16

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type
Reset value

UNDEFINED_LEGAL

pmp43cfg

Location

31:24

Description

PMP configuration for entry 43

The bits are as follows:

Name Location Description

L

31

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

30:29

Reserved Writes shall be ignored.

A

28:27

Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NA4* (2) - Naturally aligned four-byte region
* *NAPOT* (3) - Naturally aligned power of two
[when="PMP_GRANULARITY >= 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NAPOT* (3) - Naturally aligned power of two

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

X

26

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

25

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

24

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type
Reset value

UNDEFINED_LEGAL

pmp44cfg

Location

39:32

Description

PMP configuration for entry 44

The bits are as follows:

Name Location Description

L

39

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

38:37

Reserved Writes shall be ignored.

A

36:35

Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NA4* (2) - Naturally aligned four-byte region
* *NAPOT* (3) - Naturally aligned power of two
[when="PMP_GRANULARITY >= 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NAPOT* (3) - Naturally aligned power of two

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

X

34

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

33

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

32

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type
Reset value

UNDEFINED_LEGAL

pmp45cfg

Location

47:40

Description

PMP configuration for entry 45

The bits are as follows:

Name Location Description

L

47

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

46:45

Reserved Writes shall be ignored.

A

44:43

Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NA4* (2) - Naturally aligned four-byte region
* *NAPOT* (3) - Naturally aligned power of two
[when="PMP_GRANULARITY >= 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NAPOT* (3) - Naturally aligned power of two

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

X

42

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

41

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

40

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type
Reset value

UNDEFINED_LEGAL

pmp46cfg

Location

55:48

Description

PMP configuration for entry 46

The bits are as follows:

Name Location Description

L

55

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

54:53

Reserved Writes shall be ignored.

A

52:51

Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NA4* (2) - Naturally aligned four-byte region
* *NAPOT* (3) - Naturally aligned power of two
[when="PMP_GRANULARITY >= 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NAPOT* (3) - Naturally aligned power of two

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

X

50

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

49

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

48

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type
Reset value

UNDEFINED_LEGAL

pmp47cfg

Location

63:56

Description

PMP configuration for entry 47

The bits are as follows:

Name Location Description

L

63

Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.

-

62:61

Reserved Writes shall be ignored.

A

60:59

Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NA4* (2) - Naturally aligned four-byte region
* *NAPOT* (3) - Naturally aligned power of two
[when="PMP_GRANULARITY >= 2"]
* *OFF* (0) - Null region (disabled)
* *TOR* (1) - Top of range
* *NAPOT* (3) - Naturally aligned power of two

Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

X

58

When clear, instruction fetches cause an Access Fault for the matching region and privilege mode.

W

57

When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.

R

56

When clear, loads cause an Access Fault for the matching region and privilege mode.

The combination of R = 0, W = 1 is reserved.

Type
Reset value

UNDEFINED_LEGAL

Software write

This CSR may store a value that is different from what software attempts to write.

When a software write occurs (e.g., through csrrw), the following determines the written value:

pmp40cfg = if ((CSR[pmpcfg10].pmp40cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp40cfg & 0x1) == 0) && ((csr_value.pmp40cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp40cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp40cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg10].pmp40cfg;

pmp41cfg = if ((CSR[pmpcfg10].pmp41cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp41cfg & 0x1) == 0) && ((csr_value.pmp41cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp41cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp41cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg10].pmp41cfg;

pmp42cfg = if ((CSR[pmpcfg10].pmp42cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp42cfg & 0x1) == 0) && ((csr_value.pmp42cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp42cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp42cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg10].pmp42cfg;

pmp43cfg = if ((CSR[pmpcfg10].pmp43cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp43cfg & 0x1) == 0) && ((csr_value.pmp43cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp43cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp43cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg10].pmp43cfg;

pmp44cfg = if ((CSR[pmpcfg10].pmp44cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp44cfg & 0x1) == 0) && ((csr_value.pmp44cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp44cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp44cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg10].pmp44cfg;

pmp45cfg = if ((xlen() == 64) && (CSR[pmpcfg10].pmp45cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp45cfg & 0x1) == 0) && ((csr_value.pmp45cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp45cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp45cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg10].pmp45cfg;

pmp46cfg = if ((xlen() == 64) && (CSR[pmpcfg10].pmp46cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp46cfg & 0x1) == 0) && ((csr_value.pmp46cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp46cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp46cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg10].pmp46cfg;

pmp47cfg = if ((xlen() == 64) && (CSR[pmpcfg10].pmp47cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp47cfg & 0x1) == 0) && ((csr_value.pmp47cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp47cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp47cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg10].pmp47cfg;