divw
Signed 32-bit division
This instruction is defined by:
-
M, version >= M@2.0.0
This instruction is included in the following profiles:
-
RVA20S64 (Optional)
-
RVA20U64 (Mandatory)
-
RVA22S64 (Optional)
-
RVA22U64 (Mandatory)
-
RVA23S64 (Optional)
-
RVA23U64 (Mandatory)
-
RVB23S64 (Optional)
-
RVB23U64 (Mandatory)
-
RVI20U32 (Optional)
-
RVI20U64 (Optional)
Synopsis
Divide the lower 32-bits of register rs1 by the lower 32-bits of register rs2, and store the sign-extended result in rd.
The remainder is discarded.
Division by zero will put -1 into rd.
Division resulting in signed overflow (when most negative number is divided by -1) will put the most negative number into rd;
Decode Variables
Bits<5> rs2 = $encoding[24:20];
Bits<5> rs1 = $encoding[19:15];
Bits<5> rd = $encoding[11:7];idl
Execution
-
IDL
-
Sail
if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) {
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
}
Bits<32> src1 = X[rs1][31:0];
Bits<32> src2 = X[rs2][31:0];
if (src2 == 0) {
X[rd] = {XLEN{1'b1}};
} else if ((src1 == {33'b1, 31'b0}) && (src2 == 32'b1)) {
X[rd] = {33'b1, 31'b0};
} else {
Bits<32> result = $signed(src1) / $signed(src2);
Bits<1> sign_bit = result[31];
X[rd] = {{32{sign_bit}}, result};
}idl
{
if extension("M") then {
let rs1_val = X(rs1)[31..0];
let rs2_val = X(rs2)[31..0];
let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val);
let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val);
let q : int = if rs2_int == 0 then -1 else quot_round_zero(rs1_int, rs2_int);
/* check for signed overflow */
let q': int = if s & q > (2 ^ 31 - 1) then (0 - 2^31) else q;
X(rd) = sign_extend(to_bits(32, q'));
RETIRE_SUCCESS
} else {
handle_illegal();
RETIRE_FAIL
}
}sail