rolw

Rotate left word (Register)

This instruction is defined by:

  • anyOf:

    • Zbb, version >= Zbb@1.0.0

    • Zbkb, version >= Zbkb@1.0.0

This instruction is included in the following profiles:

  • RVA22S64 (Mandatory)

  • RVA22U64 (Mandatory)

  • RVA23M64 (Mandatory)

  • RVA23S64 (Mandatory)

  • RVA23U64 (Mandatory)

  • RVB23M64 (Mandatory)

  • RVB23S64 (Mandatory)

  • RVB23U64 (Mandatory)

Encoding

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Assembly format

rolw rd, rs1, rs2

Synopsis

This instruction must have data-independent timing when extension Zkt is enabled.

This instruction performs a rotate left of the least-significant word of rs1 by the amount in least-significant 5 bits of rs2. The resulting word value is sign-extended by copying bit 31 to all of the more-significant bits.

Access

M HS U VS VU

Always

Always

Always

Always

Always

Decode Variables

Bits<5> rs2 = $encoding[24:20];
Bits<5> rs1 = $encoding[19:15];
Bits<5> rd = $encoding[11:7];

Execution

  • IDL

  • Sail

if (%%LINK%func;implemented?;implemented?%%(ExtensionName::B) && (%%LINK%csr_field;misa.B;CSR[misa].B%% == 1'b0)) {
  %%LINK%func;raise;raise%%(ExceptionCode::IllegalInstruction, %%LINK%func;mode;mode%%(), $encoding);
}
XReg rs1_word = X[rs1][31:0];
XReg shamt = X[rs2][4:0];
XReg unextended_result = (rs1_word << shamt) | (rs1_word >> (32 - shamt));
X[rd] = {{32{unextended_result[31]}}, unextended_result};
{
  let rs1_val = (X(rs1))[31..0];
  let shamt = (X(rs2))[4..0];
  let result : bits(32) = match op {
    RISCV_ROLW => rs1_val <<< shamt,
    RISCV_RORW => rs1_val >>> shamt
  };
  X(rd) = sign_extend(result);
  RETIRE_SUCCESS
}

Exceptions

This instruction may result in the following synchronous exceptions:

  • IllegalInstruction