ld
Load doubleword
This instruction is defined by:
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I, version >= I@2.1.0
This instruction is included in the following profiles:
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MockProfile 64-bit S-mode (Mandatory)
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MockProfile 64-bit Unpriv (Mandatory)
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RVA20S64 (Mandatory)
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RVA20U64 (Mandatory)
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RVA22S64 (Mandatory)
-
RVA22U64 (Mandatory)
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RVA23S64 (Mandatory)
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RVA23U64 (Mandatory)
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RVB23S64 (Mandatory)
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RVB23U64 (Mandatory)
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RVI20U32 (Mandatory)
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RVI20U64 (Mandatory)
Synopsis
Load 64 bits of data into register xd from an
address formed by adding xs1 to a signed offset.
Decode Variables
Bits<12> imm = $encoding[31:20];
Bits<5> xs1 = $encoding[19:15];
Bits<5> xd = $encoding[11:7];Execution
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IDL
-
Sail
XReg virtual_address = X[xs1] + $signed(imm);
X[xd] = read_memory<64>(virtual_address, $encoding);{
let offset : xlenbits = sign_extend(imm);
/* Get the address, X(xs1) + offset.
Some extensions perform additional checks on address validity. */
match ext_data_get_addr(xs1, offset, Read(Data), width) {
Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },
Ext_DataAddr_OK(vaddr) =>
if check_misaligned(vaddr, width)
then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL }
else match translateAddr(vaddr, Read(Data)) {
TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
TR_Address(paddr, _) =>
match (width) {
BYTE =>
process_load(xd, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned),
HALF =>
process_load(xd, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned),
WORD =>
process_load(xd, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned),
DOUBLE if sizeof(xlen) >= 64 =>
process_load(xd, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned),
_ => report_invalid_width(__FILE__, __LINE__, width, "load")
}
}
}
}