zip

Bit interleave

This instruction is defined by:

  • Zbkb, version >= Zbkb@1.0.0

This instruction is included in the following profiles:

  • RVA22S64 (Optional)

  • RVA22U64 (Optional)

  • RVA23M64 (Optional)

  • RVA23S64 (Optional)

  • RVB23M64 (Optional)

  • RVB23S64 (Optional)

  • RVB23U64 (Optional)

Encoding

svg

Assembly format

zip rd, rs1

Synopsis

This instruction scatters all of the odd and even bits of a source word into the high and low halves of a destination word. It is the inverse of the unzip instruction. This instruction is available only on RV32.

Access

M HS U VS VU

Always

Always

Always

Always

Always

Decode Variables

Bits<5> rs1 = $encoding[19:15];
Bits<5> rd = $encoding[11:7];

Execution

  • IDL

  • Sail

XReg input = X[rs1];
XReg output = 0;
for (U32 i = 0; i < (%%LINK%func;xlen;xlen%%() / 2 - 1); i = i + 1) {
  output[2 * i] = input[i];
  output[2 * i + 1] = input[i + %%LINK%func;xlen;xlen%%() / 2];
}
X[rd] = output;
foreach (i from 0 to xlen/2-1) {
  X(rd)[2*i] = X(rs1)[i];
  X(rd)[2*i+1] = X(rs1)[i+xlen/2];
}