mcyclecfgh

Machine Cycle Counter Configuration High

Upper 32 bits of the 64-bit mcyclecfg CSR, used for RV32 systems to access the privilege mode filtering inhibit bits.

Attributes

Requirement

Defining extensions

Smcntrpmf

Cycle and Instret Privilege Mode Filtering

CSR Address

0x721

Length

32-bit

Privilege Mode

M

Format

mcyclecfgh format

Figure 1. mcyclecfgh format

Field Summary

Name

Location

Type

Reset Value

mcyclecfgh.MINH

30

RW

UNDEFINED_LEGAL

mcyclecfgh.SINH

29

RW

UNDEFINED_LEGAL

mcyclecfgh.UINH

28

RW

UNDEFINED_LEGAL

mcyclecfgh.VSINH

27

RW

UNDEFINED_LEGAL

mcyclecfgh.VUINH

26

RW

UNDEFINED_LEGAL

Fields

`MINH`

Location: 30
Description: If set, then counting of events in M-mode is inhibited.
Type: RW
Reset value: UNDEFINED_LEGAL

`SINH`

Location: 29
Description: If set, then counting of events in S/HS-mode is inhibited.
Type: RW
Reset value: UNDEFINED_LEGAL

`UINH`

Location: 28
Description: If set, then counting of events in U-mode is inhibited.
Type: RW
Reset value: UNDEFINED_LEGAL

`VSINH`

Location: 27
Description: If set, then counting of events in VS-mode is inhibited.
Type: RW
Reset value: UNDEFINED_LEGAL

`VUINH`

Location: 26
Description: If set, then counting of events in VU-mode is inhibited.
Type: RW
Reset value: UNDEFINED_LEGAL