mstatus

Machine Status

The mstatus register tracks and controls the hart’s current operating state.

Attributes

Defining Extension

Sm, version >= Sm@1.11.0

CSR Address

0x300

Length

* 32 when CSR[misa].MXL == 0 * 64 when CSR[misa].MXL == 1

Privilege Mode

M

Format

This CSR format changes dynamically.

mstatus Format when CSR[misa].MXL == 0
Figure 1. mstatus Format when CSR[misa].MXL == 0
mstatus Format when CSR[misa].MXL == 1
Figure 2. mstatus Format when CSR[misa].MXL == 1

Field Summary

Name Location Type Reset Value

mstatus.SD

* 31 when CSR[misa].MXL == 0 * 63 when CSR[misa].MXL == 1

[when,"(implemented?(ExtensionName::F) && HW_MSTATUS_FS_DIRTY_UPDATE != "never")"] RO-H [when,"(implemented?(ExtensionName::V) && HW_MSTATUS_VS_DIRTY_UPDATE != "never")"] RO-H [when,"else"] RO

UNDEFINED_LEGAL

mstatus.MDT

42

RW-H

UNDEFINED_LEGAL

mstatus.MPV

39

RW-H

UNDEFINED_LEGAL

mstatus.GVA

38

RW-H

0

mstatus.MBE

37

[when,"M_MODE_ENDIANNESS == "dynamic""] RW

[when,"M_MODE_ENDIANNESS != "dynamic""] RO

UNDEFINED_LEGAL

mstatus.SBE

36

[when,"S_MODE_ENDIANNESS == "dynamic""] RW

[when,"S_MODE_ENDIANNESS != "dynamic""] RO

UNDEFINED_LEGAL

mstatus.SXL

35:34

[when,"implemented?(ExtensionName::S) && SXLEN == 3264"] RW

[when,"!implemented?(ExtensionName::S) && SXLEN == 3264"] RO

UNDEFINED_LEGAL

mstatus.UXL

33:32

[when,"UXLEN == 3264"] RW

[when,"UXLEN != 3264"] RO

UNDEFINED_LEGAL

mstatus.TSR

22

RW

UNDEFINED_LEGAL

mstatus.TW

21

RW

UNDEFINED_LEGAL

mstatus.TVM

20

[when,"(CSR[misa].S == 1’b0)"] RO [when,"(CSR[misa].S != 1’b0)"] RW

UNDEFINED_LEGAL

mstatus.MXR

19

RW

UNDEFINED_LEGAL

mstatus.SUM

18

[when,"has_virt_mem?()"] RW [when,"!(has_virt_mem?())"] RO

UNDEFINED_LEGAL

mstatus.MPRV

17

[when,"misa.U == 1’b1"] RW-H

[when,"misa.U != 1’b1"] RO

0

mstatus.XS

16:15

RO

0

mstatus.FS

14:13

[when,"(CSR[misa].F == 1’b1)"] RW-H [when,"(CSR[misa].S == 1’b0 && CSR[misa].F == 1’b0)"] RO [when,"else"] [when,"MSTATUS_FS_WRITABLE"] RW

[when,"!(MSTATUS_FS_WRITABLE)"] RO

UNDEFINED_LEGAL

mstatus.MPP

12:11

RW-H

3

mstatus.VS

10:9

[when,"(CSR[misa].V == 1’b1)"] RW-H [when,"(CSR[misa].S == 1’b0 && CSR[misa].V == 1’b0)"] RO [when,"else"] [when,"MSTATUS_VS_WRITABLE"] RW

[when,"!(MSTATUS_VS_WRITABLE)"] RO

UNDEFINED_LEGAL

mstatus.SPP

8

RW-H

UNDEFINED_LEGAL

mstatus.MPIE

7

RW-H

UNDEFINED_LEGAL

mstatus.UBE

6

[when,"U_MODE_ENDIANNESS == "dynamic""] RW

[when,"U_MODE_ENDIANNESS != "dynamic""] RO

UNDEFINED_LEGAL

mstatus.SPIE

5

[when,"misa.S == 1’b1"] RW-H

[when,"misa.S != 1’b1"] RO

UNDEFINED_LEGAL

mstatus.MIE

3

RW-H

0

mstatus.SIE

1

[when,"misa.S == 1’b1"] RW-H

[when,"misa.S != 1’b1"] RO

UNDEFINED_LEGAL

Fields

SD

Location

  • 31 when CSR[misa].MXL == 0

  • 63 when CSR[misa].MXL == 1

Description

State Dirty.

Read-only bit that summarizes whether either the FS, XS, or VS fields signal the presence of some dirty state.

Type

RO-H

RO-H

RO

Reset value

UNDEFINED_LEGAL

MDT

Location

42

Description

Machine Disable Trap

Written to 1 when entering M-mode from an exception/interrupt. When returning via an MRET instruction, the bit is written to 0. On reset in set to 1, and software should write it to 0 when boot sequence is done. When mstatus.MDT=1, direct write by CSR instruction cannot set mstatus.MIE to 1, if not written together.

Type

RW-H

Reset value

UNDEFINED_LEGAL

MPV

Location

39

Description

Machine Previous Virtualization mode

Written with the prior virtualization mode when entering M-mode from an exception/interrupt. When returning via an MRET instruction, the virtualization mode becomes the value of MPV unless MPP=3, in which case the virtualization mode is always 0. Can also be written by software.

Type

RW-H

Reset value

UNDEFINED_LEGAL

GVA

Location

38

Description

Guest Virtual Address

When a trap is taken and a guest virtual address is written into mtval, GVA is set. When a trap is taken and a guest virtual address is written into mtval, GVA is cleared.

Type

RW-H

Reset value

0

MBE

Location

37

Description

M-mode Big Endian

Controls the endianness of data M-mode (0 = little, 1 = big). Instructions are always little endian, regardless of the data setting.

Since the CPU does not support big endian, this is hardwired to 0.

Since the CPU does not support little endian, this is hardwired to 1.

Type

RW

RO

Reset value

UNDEFINED_LEGAL

SBE

Location

36

Description

S-mode Big Endian

Controls the endianness of S-mode (0 = little, 1 = big). Instructions are always little endian, regardless of the data setting.

Since the CPU does not support big endian, this is hardwired to 0.

Since the CPU does not support little endian, this is hardwired to 1.

Type

RW

RO

Reset value

UNDEFINED_LEGAL

SXL

Location

35:34

Description

S-mode XLEN

Sets the effective XLEN for S-mode (0 = 32-bit, 1 = 64-bit, 2 = 128-bit [reserved]).

Since the CPU only supports SXLEN==32, this is hardwired to 0.

Since the CPU only supports SXLEN==64, this is hardwired to 1.

It is not valid to have SXLEN less than UXLEN.

It is UNDEFINED_LEGAL what will happen if a software sets mstatus.SXL to be greater than mstatus.UXL.

It is UNDEFINED_LEGAL to set the MSB of SXL.

Type

RW

RO

Reset value

UNDEFINED_LEGAL

UXL

Location

33:32

Description

U-mode XLEN.

Sets the effective XLEN for U-mode (0 = 32-bit, 1 = 64-bit, 2 = 128-bit [reserved]).

Since the CPU only supports UXLEN==32, this is hardwired to 0.

Since the CPU only supports UXLEN==64, this is hardwired to 1.

It is not valid to have SXLEN less than UXLEN.

It is UNDEFINED_LEGAL what will happen if a software sets mstatus.SXL to be greater than mstatus.UXL.

It is UNDEFINED_LEGAL to set the MSB of UXL.

Type

RW

RO

Reset value

UNDEFINED_LEGAL

TSR

Location

22

Description

Trap SRET

When 1, attempts to execute the sret instruction while executing in HS/S-mode will raise an Illegal Instruction exception.

Does not affect the behavior of sret in VS_mode (see hstatus.VTSR).

Type

RW

Reset value

UNDEFINED_LEGAL

TW

Location

21

Description

Timeout Wait

When 1, the WFI instruction will raise an Illegal Instruction trap after an implementaion-defined wait period when executed in a mode other than M-mode.

When 0, the wfi instruction is permitted to wait forever in (H)S-mode but must trap after an implementation-defined wait period in U-mode.

Type

RW

Reset value

UNDEFINED_LEGAL

TVM

Location

20

Description

Trap Virtual Memory.

When 1, an Illegal Instruction trap occurs when

Notably, mstatus.TVM does not cause

*hfence.vvma, sfence.w.inval, or sfence.inval.ir to trap. * Any additional traps in VS-mode (controlled via hstatus.VTVM instead).

Type

RO

RW

Reset value

UNDEFINED_LEGAL

MXR

Location

19

Description

Make eXecutable Readable.

When 1, loads from pages marked readable or executable are allowed. When 0, loads from pages marked executable raise a Page Fault exception.

Type

RW

Reset value

UNDEFINED_LEGAL

SUM

Location

18

Description

permit Supervisor Memory Access.

When 0, an S-mode read or an M-mode read with mstatus.MPRV=1 and mstatus.MPP=01 to a 'U' (user) page will cause an ILLEGAL INSTRUCTION exception.

Type

RW

RO

Reset value

UNDEFINED_LEGAL

MPRV

Location

17

Description

Modify PRiVilege.

When 1, loads and stores behave as if the current virtualization mode:privilege level was mstatus.MPV:mstatus.MPP.

mstatus.MPRV is cleared on any exception return (mret or sret instruction, regardless of the trap handler privilege mode).

Type

RW-H

RO

Reset value

0

XS

Location

16:15

Description

Custom (X) extension context Status

Summarizes the current state of any custom extension state. Either 0 - Off, 1 - Initial, 2 - Clean, 3 - Dirty. Since there are no custom extensions in the base spec, this field is read-only 0.

Type

RO

Reset value

0

FS

Location

14:13

Description

Floating point context status.

When 0, floating point instructions (from F and D extensions) are disabled, and cause ILLEGAL INSTRUCTION exceptions. When a floating point register, or the fCSR register is written, FS obtains the value 3. Values 1 and 2 are valid write values for software, but are not interpreted by hardware other than to possibly enable a previously-disabled floating point unit.

Type

RW-H

RO

RW

RO

Reset value

UNDEFINED_LEGAL

MPP

Location

12:11

Description

M-mode Previous Privilege.

Written by hardware in two cases:

  • Written with the prior nominal privilege level when entering M-mode from an exception/interrupt.

  • Written with 0 when executing an mret instruction to return from an exception in M-mode.

Can also be written by software without immediate side-effect.

Affects execution in two cases:

  • On a return from an exception from M-mode, the machine will enter the privilege level stored in MPP before clearing the field.

  • When mstatus.MPRV is set, loads and stores behave as if the current privilege level were MPP.

    Type

    RW-H

    Reset value

    3

VS

Location

10:9

Description

Vector context status.

When 0, vector instructions (from the V extension) are disabled, and cause ILLEGAL INSTRUCTION exceptions. When a vector register or vector CSR is written, VS obtains the value 3. Values 1 and 2 are valid write values for software, but are not interpreted by hardware other than to possibly enable a previously-disabled vector unit.

Type

RW-H

RO

RW

RO

Reset value

UNDEFINED_LEGAL

SPP

Location

8

Description

S-mode Previous Privilege

Written by hardware in two cases:

  • Written with the prior nominal privilege level when entering (H)S-mode from an exception/interrupt.

  • Written with 0 when executing an sret instruction to return from an exception in (H)S-mode or (unlikely) M-mode.

Can also be written by software without immediate side-effect.

Affects execution in one case:

  • On a return from an exception using the sret instruction in (H)S-mode or (unlikely) M-mode, the machine will enter the privilege level stored in SPP before clearing the field.

Notably, mstatus.SPP does not affect exception return in VS-mode (see vsstatus.SPP).

Type

RW-H

Reset value

UNDEFINED_LEGAL

MPIE

Location

7

Description

M-mode Previous Interrupt Enable

Written by hardware in two cases:

  • Written with prior value of mstatus.MIE when entering M-mode from an exception/interrupt.

  • Written with the value 1 when returning from an exception in M-mode (via the mret instruction).

Can also be written by software without immediate side effect.

Other than serving as a record of nested traps as described above, mstatus.MPIE does not affect execution.

Type

RW-H

Reset value

UNDEFINED_LEGAL

UBE

Location

6

Description

U-mode Big Endian

Controls the endianness of U-mode (0 = little, 1 = big). Instructions are always little endian, regardless of the data setting.

Since the CPU does not support big endian in U-mode, this is hardwired to 0.

Since the CPU does not support little endian in U-mode, this is hardwired to 1.

Type

RW

RO

Reset value

UNDEFINED_LEGAL

SPIE

Location

5

Description

S-mode Previous Interrupt Enable

Written by hardware in two cases:

  • Written with prior value of mstatus.SIE when entering (H)S-mode from an exception/interrupt.

  • Written with the value 1 when returning from an exception via the sret instruction in (H)S-mode or (unlikely) M-mode.

Can also be written by software without immediate side effect.

Other than serving as a record of nested traps as described above, mstatus.SPIE does not affect execution.

Type

RW-H

RO

Reset value

UNDEFINED_LEGAL

MIE

Location

3

Description

M-mode Interrupt Enable

Written by hardware in two cases:

  • Written with the value 0 when entering M-mode from an exception/interrupt.

  • Written with the prior value of mstatus.MPIE when returning from an exception in M-mode (via mret).

Affects execution by:

  • When 0, all interrupts are disabled when the current privilege level is M.

  • When 1, interrupts that are not otherwise disabled with a field in mie are enabled.

    Type

    RW-H

    Reset value

    0

SIE

Location

1

Description

S-mode Interrupt Enable

Written by hardware in two cases:

  • Written with the value 0 when entering (H)S-mode from an exception/interrupt.

  • Written with the prior value of mstatus.SPIE when returning from an exception via sret in (H)S-mode or (unlikely) M-mode.

Affects execution by:

  • When 0, all (H)S-mode interrupts are disabled when the current privilege level is (H)S (M-mode interrupts are still enabled).

  • When 1, (H)S-mode interrupts that are not otherwise disabled with a field in sie are enabled.

    Type

    RW-H

RO

Reset value

UNDEFINED_LEGAL

Software write

This CSR may store a value that is different from what software attempts to write.

When a software write occurs (e.g., through csrrw), the following determines the written value:

SD = csr_value.SD
MDT = csr_value.MDT
MPV = csr_value.MPV
GVA = csr_value.GVA
MBE = csr_value.MBE
SBE = csr_value.SBE
SXL = if (csr_value.SXL < csr_value.UXL) {
  return UNDEFINED_LEGAL_DETERMINISTIC;
} else if (csr_value.SXL > 1) {
  # SXL != [0, 1] is not defined (2 reserved for RV128, but that isn't ratified)
  return UNDEFINED_LEGAL_DETERMINISTIC;
} else {
  return csr_value.SXL;
}

UXL = if (csr_value.SXL < csr_value.UXL) {
  return UNDEFINED_LEGAL_DETERMINISTIC;
} else if (csr_value.UXL > 1) {
  # UXL != [0, 1] is not defined (2 reserved for RV128, but that isn't ratified)
  return UNDEFINED_LEGAL_DETERMINISTIC;
} else {
  return csr_value.UXL;
}

TSR = csr_value.TSR
TW = csr_value.TW
TVM = if (CSR[misa].S == 1'b0) {
  return 0;
} else if (MSTATUS_TVM_IMPLEMENTED) {
  return csr_value.TVM;
} else {
  return 0;
}

MXR = csr_value.MXR
SUM = csr_value.SUM
MPRV = csr_value.MPRV
XS = csr_value.XS
FS = if (CSR[misa].F == 1'b1){
  return ary_includes?<$array_size(MSTATUS_FS_LEGAL_VALUES), 2>(MSTATUS_FS_LEGAL_VALUES, csr_value.FS) ? csr_value.FS : UNDEFINED_LEGAL_DETERMINISTIC;
} else if ((CSR[misa].S == 1'b0) && (CSR[misa].F == 1'b0)) {
  # must be read-only-0
  return 0;
} else {
  # there will be no hardware update in this case because we know the F extension isn't implemented
  return ary_includes?<$array_size(MSTATUS_FS_LEGAL_VALUES), 2>(MSTATUS_FS_LEGAL_VALUES, csr_value.FS) ? csr_value.FS : UNDEFINED_LEGAL_DETERMINISTIC;
}

MPP = if (csr_value.MPP == 2'b01 && !implemented?(ExtensionName::S)) {
  return UNDEFINED_LEGAL_DETERMINISTIC;
} else if (csr_value.MPP == 2'b00 && !implemented?(ExtensionName::U)) {
  return UNDEFINED_LEGAL_DETERMINISTIC;
} else if (csr_value.MPP == 2'b10) {
  # never a valid value
  return UNDEFINED_LEGAL_DETERMINISTIC;
} else {
  return csr_value.MPP;
}

VS = if (CSR[misa].V == 1'b1){
  return ary_includes?<$array_size(MSTATUS_VS_LEGAL_VALUES), 2>(MSTATUS_VS_LEGAL_VALUES, csr_value.VS) ? csr_value.VS : UNDEFINED_LEGAL_DETERMINISTIC;
} else if ((CSR[misa].S == 1'b0) && (CSR[misa].V == 1'b0)) {
  # must be read-only-0
  return 0;
} else {
  # there will be no hardware update in this case because we know the V extension isn't implemented
  return ary_includes?<$array_size(MSTATUS_VS_LEGAL_VALUES), 2>(MSTATUS_VS_LEGAL_VALUES, csr_value.VS) ? csr_value.VS : UNDEFINED_LEGAL_DETERMINISTIC;
}

SPP = if (csr_value.SPP == 2'b10) {
  return UNDEFINED_LEGAL_DETERMINISTIC;
} else {
  return csr_value.SPP;
}

MPIE = csr_value.MPIE
UBE = csr_value.UBE
SPIE = csr_value.SPIE
MIE = csr_value.MIE
SIE = csr_value.SIE