sha512sum0r :: RISC-V ISA Manual

Assembly format

sha512sum0r rd, rs1, rs2

This instruction must have data-independent timing when extension Zkt is enabled.

No description available.

Bits<5> rs2 = $encoding[24:20];
Bits<5> rs1 = $encoding[19:15];
Bits<5> rd = $encoding[11:7];

M	HS	U	VS	VU
Always	Always	Always	Always	Always

M

HS

U

VS

VU

Always