fadd.s

Single-precision floating-point addition

This instruction is defined by:

  • F, version >= 0

This instruction is included in the following profiles:

  • RVA20S64 (Optional)

  • RVA20U64 (Mandatory)

  • RVA22S64 (Optional)

  • RVA22U64 (Mandatory)

  • RVA23S64 (Optional)

  • RVA23U64 (Mandatory)

  • RVB23S64 (Optional)

  • RVB23U64 (Mandatory)

  • RVI20U32 (Optional)

  • RVI20U64 (Optional)

Encoding

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Assembly format

fadd.s fd, fs1, fs2, rm

Synopsis

This instruction must have data-independent timing when extension Zkt is enabled.

Do the single-precision floating-point addition of fs1 and fs2 and store the result in fd. rm is the dynamic Rounding Mode.

Access

M HS U VS VU

Always

Always

Always

Always

Always

Decode Variables

Bits<5> fs2 = $encoding[24:20];
Bits<5> fs1 = $encoding[19:15];
Bits<3> rm = $encoding[14:12];
Bits<5> fd = $encoding[11:7];

Execution

  • IDL

  • Sail

RoundingMode mode = rm_to_mode(X[rm], $encoding);
X[fd] = f32_add(X[fs1], X[fs2], mode);
{
  let rs1_val_32b = F_or_X_S(rs1);
  let rs2_val_32b = F_or_X_S(rs2);
  match (select_instr_or_fcsr_rm (rm)) {
    None() => { handle_illegal(); RETIRE_FAIL },
    Some(rm') => {
      let rm_3b = encdec_rounding_mode(rm');
      let (fflags, rd_val_32b) : (bits(5), bits(32)) = match op {
        FADD_S  => riscv_f32Add (rm_3b, rs1_val_32b, rs2_val_32b),
        FSUB_S  => riscv_f32Sub (rm_3b, rs1_val_32b, rs2_val_32b),
        FMUL_S  => riscv_f32Mul (rm_3b, rs1_val_32b, rs2_val_32b),
        FDIV_S  => riscv_f32Div (rm_3b, rs1_val_32b, rs2_val_32b)
      };
      accrue_fflags(fflags);
      F_or_X_S(rd) = rd_val_32b;
      RETIRE_SUCCESS
    }
  }
}

Exceptions

This instruction may result in the following synchronous exceptions:

  • IllegalInstruction