c.fsw

Store single-precision

This instruction is defined by:

  • anyOf:

    • allOf:

      • C, version >= C@2.0.0

      • F, version >= F@2.2.0

    • Zcf, version >= Zcf@1.0.0

This instruction is included in the following profiles:

  • RVA20S64 (Optional)

  • RVA20U64 (Mandatory)

  • RVA22S64 (Optional)

  • RVA22U64 (Mandatory)

  • RVA23S64 (Optional)

  • RVA23U64 (Mandatory)

  • RVB23S64 (Optional)

  • RVB23U64 (Mandatory)

  • RVI20U32 (Optional)

  • RVI20U64 (Optional)

Encoding

svg

Assembly format

c.fsw rs2, imm(rs1)

Synopsis

Stores a single precision floating-point value in register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1. It expands to fsw rs2, offset(rs1).

Access

M HS U VS VU

Always

Always

Always

Always

Always

Decode Variables

Bits<7> imm = {$encoding[5], $encoding[12:10], $encoding[6], 2'd0};
Bits<3> rs2 = $encoding[4:2];
Bits<3> rs1 = $encoding[9:7];

Execution

  • IDL

if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
  raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
}
XReg virtual_address = X[creg2reg(rs1)] + imm;
write_memory<32>(virtual_address, X[creg2reg(rs2)][31:0], $encoding);

Exceptions

This instruction may result in the following synchronous exceptions:

  • IllegalInstruction

  • LoadAccessFault

  • StoreAmoAccessFault

  • StoreAmoAddressMisaligned

  • StoreAmoPageFault