hinval.vvma

Invalidate cached address translations

This instruction is defined by:

  • allOf:

    • Svinval, version >= Svinval@1.0.0

    • H, version >= H@1.0.0

This instruction is included in the following profiles:

  • RVA22S64 (Mandatory)

  • RVA23S64 (Mandatory)

  • RVB23S64 (Mandatory)

Encoding

svg

Assembly format

hinval.vvma rs1, rs2

Synopsis

hinval.vvma has the same semantics as sinval.vma except that it combines with sfence.w.inval and sfence.inval.ir to replace hfence.vvma.

Access

M HS U VS VU

Always

Always

Never

Never

Never

Decode Variables

Bits<5> rs2 = $encoding[24:20];
Bits<5> rs1 = $encoding[19:15];

Execution

  • IDL

XReg vaddr = X[rs1];
Bits<ASID_WIDTH> asid = X[rs2][ASID_WIDTH - 1:0];
Bits<VMID_WIDTH> vmid = CSR[hgatp].VMID;
if (mode() == PrivilegeMode::U) {
  raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
}
if ((CSR[misa].H == 1) && (mode() == PrivilegeMode::VS || mode() == PrivilegeMode::VU)) {
  raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
}
VmaOrderType vma_type;
vma_type.vsmode = true;
vma_type.single_vmid = true;
vma_type.vmid = vmid;
if ((rs1 == 0) && (rs2 == 0)) {
  vma_type.global = true;
  invalidate_translations(vma_type);
} else if ((rs1 == 0) && (rs2 != 0)) {
  vma_type.single_asid = true;
  vma_type.asid = asid;
  invalidate_translations(vma_type);
} else if ((rs1 != 0) && (rs2 == 0)) {
  if (canonical_vaddr?(vaddr)) {
    vma_type.single_vaddr = true;
    vma_type.vaddr = vaddr;
    invalidate_translations(vma_type);
  }
} else {
  if (canonical_vaddr?(vaddr)) {
    vma_type.single_asid = true;
    vma_type.asid = asid;
    vma_type.single_vaddr = true;
    vma_type.vaddr = vaddr;
    invalidate_translations(vma_type);
  }
}

Exceptions

This instruction may result in the following synchronous exceptions:

  • IllegalInstruction

  • VirtualInstruction