c.fld

Load double-precision

This instruction is defined by:

  • anyOf:

    • allOf:

      • C, version >= C@2.0.0

      • D, version >= D@2.2.0

    • Zcd, version >= Zcd@1.0.0

This instruction is included in the following profiles:

  • RVA20S64 (Optional)

  • RVA20U64 (Mandatory)

  • RVA22S64 (Optional)

  • RVA22U64 (Mandatory)

  • RVA23S64 (Optional)

  • RVA23U64 (Mandatory)

  • RVB23S64 (Optional)

  • RVB23U64 (Mandatory)

  • RVI20U32 (Optional)

  • RVI20U64 (Optional)

Encoding

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Assembly format

c.fld rd, imm(rs1)

Synopsis

Loads a double precision floating-point value from memory into register rd. It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1. It expands to fld rd, offset(rs1).

Access

M HS U VS VU

Always

Always

Always

Always

Always

Decode Variables

Bits<8> imm = {$encoding[6:5], $encoding[12:10], 3'd0};
Bits<3> rd = $encoding[4:2];
Bits<3> rs1 = $encoding[9:7];

Execution

  • IDL

if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
  raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
}
XReg virtual_address = X[creg2reg(rs1)] + imm;
X[creg2reg(rd)] = sext(read_memory<64>(virtual_address, $encoding), 64);

Exceptions

This instruction may result in the following synchronous exceptions:

  • IllegalInstruction

  • LoadAccessFault

  • LoadAddressMisaligned

  • LoadPageFault