c.beqz

Branch if Equal Zero

This instruction is defined by:

  • anyOf:

    • C, version >= 0

    • Zca, version >= 0

This instruction is included in the following profiles:

Encoding

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Assembly format

c.beqz rs1, imm

Synopsis

C.BEQZ performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. It can therefore target a ±256 B range. C.BEQZ takes the branch if the value in register rs1' is zero. It expands to beq rs1, x0, offset.

Access

M HS U VS VU

Always

Always

Always

Always

Always

Decode Variables

Bits<8> imm = {$encoding[12], $encoding[6:5], $encoding[2], $encoding[11:10], $encoding[4:3]};
Bits<3> rs1 = $encoding[9:7];

Execution

  • IDL

  • Sail

if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
  raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
}
if (X[rs1] != 0) {
  jump($pc + imm);
}
{
  let rs1_val = X(rs1);
  let rs2_val = X(0);
  let taken : bool = match op {
    RISCV_BEQ  => rs1_val == rs2_val,
    RISCV_BNE  => rs1_val != rs2_val,
    RISCV_BLT  => rs1_val <_s rs2_val,
    RISCV_BGE  => rs1_val >=_s rs2_val,
    RISCV_BLTU => rs1_val <_u rs2_val,
    RISCV_BGEU => rs1_val >=_u rs2_val
  };
  let t : xlenbits = PC + sign_extend(imm);
  if taken then {
    /* Extensions get the first checks on the prospective target address. */
    match ext_control_check_pc(t) {
      Ext_ControlAddr_Error(e) => {
        ext_handle_control_check_error(e);
        RETIRE_FAIL
      },
      Ext_ControlAddr_OK(target) => {
        if bit_to_bool(target[1]) & not(extension("C")) then {
          handle_mem_exception(target, E_Fetch_Addr_Align());
          RETIRE_FAIL;
        } else {
          set_next_pc(target);
          RETIRE_SUCCESS
        }
      }
    }
  } else RETIRE_SUCCESS
}

Exceptions

This instruction may result in the following synchronous exceptions:

  • IllegalInstruction

  • InstructionAddressMisaligned