sinval.vma
Invalidate cached address translations
The sinval.vma instruction invalidates any address-translation cache entries that an sfence.vma instruction with the same values of rs1 and rs2 would invalidate. However, unlike sfence.vma, sinval.vma instructions are only ordered with respect to sfence.vma, sfence.w.inval, and sfence.inval.ir instructions as defined below.
Execution
-
IDL
XReg vaddr = X[rs1];
Bits<ASID_WIDTH> asid = X[rs2][ASID_WIDTH - 1:0];
if (mstatus.TVM == 1 && mode() == PrivilegeMode::S) || (mode() == PrivilegeMode::VS) {
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
}
if (misa.H == 1 && hstatus.VTVM == 1 && mode() == PrivilegeMode::VS) {
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
}
if (mode() == PrivilegeMode::U) {
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
}
if (misa.H == 1 && mode() == PrivilegeMode::VU) {
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
}
VmaOrderType vma_type;
if (misa.H == 1 && mode() == PrivilegeMode::VS) {
vma_type.vsmode = true;
vma_type.single_vmid = true;
vma_type.vmid = hgatp.VMID;
} else {
vma_type.smode = true;
}
if ((rs1 == 0) && (rs2 == 0)) {
vma_type.global = true;
invalidate_translations(vma_type);
} else if ((rs1 == 0) && (rs2 != 0)) {
vma_type.single_asid = true;
vma_type.asid = asid;
invalidate_translations(vma_type);
} else if ((rs1 != 0) && (rs2 == 0)) {
if (canonical_vaddr?(vaddr)) {
vma_type.single_vaddr = true;
vma_type.vaddr = vaddr;
invalidate_translations(vma_type);
}
} else {
if (canonical_vaddr?(vaddr)) {
vma_type.single_asid = true;
vma_type.asid = asid;
vma_type.single_vaddr = true;
vma_type.vaddr = vaddr;
invalidate_translations(vma_type);
}
}