Architectural Parameters
The following 144 parameters are defined in this manual:
Name | Type | Extension(s) | Description | ||||||||||||||
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ARCH_ID |
64-bit integer |
Vendor-specific architecture ID in marchid |
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ASID_WIDTH |
0 to 16 |
Number of implemented ASID bits. Maximum is 16 for XLEN==64, and 9 for XLEN==32 |
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CONFIG_PTR_ADDRESS |
integer |
Physical address of the unified discovery configuration data structure. This address is reported in the mconfigptr CSR. TODO: GitHub issue 53 |
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COUNTINHIBIT_EN |
32-element array where: |
Indicates which hardware performance monitor counters can be disabled from mcountinhibit. An unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false, it would be illegal to set COUNTINHIBIT_EN[3] to true. COUNTINHIBIT_EN[1] can never be true, since it corresponds to mcountinhibit, which is always read-only-0. COUNTINHIBIT_EN[3:31] must all be false if Zihpm is not implemented. |
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GSTAGE_MODE_BARE |
boolean |
Whether or not writing mode=Bare is supported in the hgatp register. |
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HCOUNTENABLE_EN |
32-element array of boolean |
Indicates which counters can delegated via hcounteren An unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false, it would be illegal to set HCOUNTENABLE_EN[3] to true. |
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HPM_COUNTER_EN |
32-element array where: |
List of HPM counters that are enabled. There is one entry for each hpmcounter. The first three entries must be false (as they correspond to CY, IR, TM in, e.g. |
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HPM_EVENTS |
array of 58-bit integer |
List of defined event numbers that can be written into hpmeventN |
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HW_MSTATUS_FS_DIRTY_UPDATE |
[never, precise, imprecise] |
Indicates whether or not hardware will write to mstatus.FS Values are:
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HW_MSTATUS_VS_DIRTY_UPDATE |
[never, precise, imprecise] |
Indicates whether or not hardware will write to mstatus.VS Values are:
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IGNORE_INVALID_VSATP_MODE_WRITES_WHEN_V_EQ_ZERO |
boolean |
Whether writes from M-mode, U-mode, or S-mode to vsatp with an illegal mode setting are ignored (as they are with satp), or if they are treated as WARL, leading to undpredictable behavior. |
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IMP_ID |
64-bit integer |
Vendor-specific implementation ID in mimpid |
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LRSC_FAIL_ON_NON_EXACT_LRSC |
boolean |
Whether or not a Store Conditional fails if its physical address and size do not exactly match the physical address and size of the last Load Reserved in program order (independent of whether or not the SC is in the current reservation set) |
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LRSC_FAIL_ON_VA_SYNONYM |
boolean |
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LRSC_MISALIGNED_BEHAVIOR |
[always raise misaligned exception, always raise access fault, custom] |
What to do when an LR/SC address is misaligned and MISALIGNED_AMO == false.
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LRSC_RESERVATION_STRATEGY |
[reserve naturally-aligned 64-byte region, reserve naturally-aligned 128-byte region, reserve exactly enough to cover the access, custom] |
Strategy used to handle reservation sets.
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MCOUNTENABLE_EN |
32-element array of boolean |
Indicates which counters can be delegated via mcounteren. An unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false, it would be illegal to set MCOUNTENABLE_EN[3] to true. |
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MISALIGNED_AMO |
boolean |
whether or not the implementation supports misaligned atomics in main memory |
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MISALIGNED_LDST |
boolean |
Does the implementation perform non-atomic misaligned loads and stores to main memory (does not affect misaligned support to device memory)? If not, the implementation always throws a misaligned exception. |
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MISALIGNED_LDST_EXCEPTION_PRIORITY |
[low, high] |
The relative priority of a load/store/AMO exception vs. load/store/AMO page-fault or access-fault exceptions. May be one of:
MISALIGNED_LDST_EXCEPTION_PRIORITY cannot be "high" when MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE is non-zero, since the atomicity of an access cannot be determined in that case until after address translation. |
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MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE |
[0, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096] |
The maximum granule size, in bytes, that the hart can atomically perform a misaligned load/store/AMO without raising a Misaligned exception. When MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE is 0, the hart cannot atomically perform a misaligned load/store/AMO. When a power of two, the hart can atomically load/store/AMO a misaligned access that is fully contained in a MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE-aligned region.
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MISALIGNED_SPLIT_STRATEGY |
[by_byte, custom] |
When misaligned accesses are supported, this determines the order in the implementation appears to process the load/store, which determines how/which exceptions will be reported Options:
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MISA_CSR_IMPLEMENTED |
boolean |
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MSTATUS_FS_LEGAL_VALUES |
at most 4-element array of [0, 1, 2, 3] |
The set of values that mstatus.FS will accept from a software write. |
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MSTATUS_FS_WRITEABLE |
boolean |
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MSTATUS_TVM_IMPLEMENTED |
boolean |
Whether or not mstatus.TVM is implemented. When not implemented mstatus.TVM will be read-only-zero. |
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MSTATUS_VS_LEGAL_VALUES |
at most 4-element array of [0, 1, 2, 3] |
The set of values that mstatus.VS will accept from a software write. |
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MSTATUS_VS_WRITEABLE |
boolean |
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MTVAL_WIDTH |
≤ 64 |
The number of implemented bits in the mtval CSR. This is the CSR that may be written when a trap is taken into M-mode with exception-specific information to assist software in handling the trap (e.g., address associated with exception). Must be greater than or equal to max( |
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MTVEC_BASE_ALIGNMENT_DIRECT |
≥ 4 |
Byte alignment for mtvec.BASE when mtvec.MODE is Direct. Cannot be less than 4-byte alignment. |
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MTVEC_BASE_ALIGNMENT_VECTORED |
≥ 4 |
Byte alignment for mtvec.BASE when mtvec.MODE is Vectored. Cannot be less than 4-byte alignment. |
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MTVEC_MODES |
1-element to 2-element array of [0, 1] |
Modes supported by mtvec.MODE. If only one, it is assumed to be read-only with that value. |
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MUTABLE_MISA_A |
boolean |
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MUTABLE_MISA_B |
boolean |
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MUTABLE_MISA_D |
boolean |
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MUTABLE_MISA_F |
boolean |
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MUTABLE_MISA_H |
boolean |
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MUTABLE_MISA_M |
boolean |
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MUTABLE_MISA_S |
boolean |
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MUTABLE_MISA_U |
boolean |
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MUTABLE_MISA_V |
boolean |
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M_MODE_ENDIANESS |
[little, big, dynamic] |
Endianess of data in M-mode. Can be one of:
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NUM_EXTERNAL_GUEST_INTERRUPTS |
1 to 63 |
Number of supported virtualized guest interrupts Corresponds to the |
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NUM_PMP_ENTRIES |
0 to 64 |
Number of implemented PMP entries. Can be any value between 0-64, inclusive. The architecture mandates that the number of implemented PMP registers must appear to be 0, 16, or 64. Therefore, pmp registers will behave as follows according to NUN_PMP_ENTRIES:
When NUM_PMP_ENTRIES is not exactly 0, 16, or 64, some extant pmp registers, and associated pmpNcfg, will be read-only zero (but will never cause an exception). |
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PHYS_ADDR_WIDTH |
≤ 64 |
Number of bits in the physical address space. |
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PMA_GRANULARITY |
2 to 66 |
log2 of the smallest supported PMA region. Generally, for systems with an MMU, should not be smaller than 12, as that would preclude caching PMP results in the TLB along with virtual memory translations |
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PMP_GRANULARITY |
2 to 66 |
log2 of the smallest supported PMP region. Generally, for systems with an MMU, should not be smaller than 12, as that would preclude caching PMP results in the TLB along with virtual memory translations Note that PMP_GRANULARITY is equal to G+2 (not G) as described in the privileged architecture. |
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PRECISE_SYNCHRONOUS_EXCEPTIONS |
boolean |
Whether or not all synchronous exceptions are precise. If false, any exception not otherwise mandated to precise (e.g., PMP violation) will cause execution to enter an unpredictable state. |
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REPORT_CAUSE_IN_MTVAL_ON_LANDING_PAD_SOFTWARE_CHECK |
boolean |
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REPORT_CAUSE_IN_MTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK |
boolean |
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REPORT_CAUSE_IN_STVAL_ON_LANDING_PAD_SOFTWARE_CHECK |
boolean |
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REPORT_CAUSE_IN_STVAL_ON_SHADOW_STACK_SOFTWARE_CHECK |
boolean |
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REPORT_CAUSE_IN_VSTVAL_ON_LANDING_PAD_SOFTWARE_CHECK |
boolean |
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REPORT_CAUSE_IN_VSTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK |
boolean |
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REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION |
boolean |
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REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION |
boolean |
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REPORT_ENCODING_IN_VSTVAL_ON_ILLEGAL_INSTRUCTION |
boolean |
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REPORT_GPA_IN_TVAL_ON_INSTRUCTION_GUEST_PAGE_FAULT |
boolean |
Whether or not GPA >> 2 is written into htval/mtval2 when an instruction guest page fault occurs. If false, 0 will be written into htval/mtval2 on an instruction guest page fault. |
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REPORT_GPA_IN_TVAL_ON_INTERMEDIATE_GUEST_PAGE_FAULT |
boolean |
Whether or not GPA >> 2 is written into htval/mtval2 when a guest page fault occurs while walking a VS-mode page table. If false, 0 will be written into htval/mtval2 on an intermediate guest page fault. |
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REPORT_GPA_IN_TVAL_ON_LOAD_GUEST_PAGE_FAULT |
boolean |
Whether or not GPA >> 2 is written into htval/mtval2 when a load guest page fault occurs. If false, 0 will be written into htval/mtval2 on a load guest page fault. |
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REPORT_GPA_IN_TVAL_ON_STORE_AMO_GUEST_PAGE_FAULT |
boolean |
Whether or not GPA >> 2 is written into htval/mtval2 when a store/amo guest page fault occurs. If false, 0 will be written into htval/mtval2 on a store/amo guest page fault. |
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REPORT_VA_IN_MTVAL_ON_BREAKPOINT |
boolean |
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REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT |
boolean |
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REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED |
boolean |
When true, mtval is written with the virtual PC when an instruction fetch is misaligned. When false, mtval is written with 0 when an instruction fetch is misaligned. Note that when IALIGN=16 (i.e., when the C or one of the |
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REPORT_VA_IN_MTVAL_ON_INSTRUCTION_PAGE_FAULT |
boolean |
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REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT |
boolean |
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REPORT_VA_IN_MTVAL_ON_LOAD_MISALIGNED |
boolean |
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REPORT_VA_IN_MTVAL_ON_LOAD_PAGE_FAULT |
boolean |
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REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT |
boolean |
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REPORT_VA_IN_MTVAL_ON_STORE_AMO_MISALIGNED |
boolean |
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REPORT_VA_IN_MTVAL_ON_STORE_AMO_PAGE_FAULT |
boolean |
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REPORT_VA_IN_STVAL_ON_BREAKPOINT |
boolean |
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REPORT_VA_IN_STVAL_ON_INSTRUCTION_ACCESS_FAULT |
boolean |
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REPORT_VA_IN_STVAL_ON_INSTRUCTION_MISALIGNED |
boolean |
When true, stval is written with the virtual PC when an instruction fetch is misaligned. When false, stval is written with 0 when an instruction fetch is misaligned. Note that when IALIGN=16 (i.e., when the C or one of the |
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REPORT_VA_IN_STVAL_ON_INSTRUCTION_PAGE_FAULT |
boolean |
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REPORT_VA_IN_STVAL_ON_LOAD_ACCESS_FAULT |
boolean |
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REPORT_VA_IN_STVAL_ON_LOAD_MISALIGNED |
boolean |
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REPORT_VA_IN_STVAL_ON_LOAD_PAGE_FAULT |
boolean |
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REPORT_VA_IN_STVAL_ON_STORE_AMO_ACCESS_FAULT |
boolean |
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REPORT_VA_IN_STVAL_ON_STORE_AMO_MISALIGNED |
boolean |
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REPORT_VA_IN_STVAL_ON_STORE_AMO_PAGE_FAULT |
boolean |
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REPORT_VA_IN_VSTVAL_ON_BREAKPOINT |
boolean |
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REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_ACCESS_FAULT |
boolean |
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REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_MISALIGNED |
boolean |
When true, vstval is written with the virtual PC when an instruction fetch is misaligned. When false, vstval is written with 0 when an instruction fetch is misaligned. Note that when IALIGN=16 (i.e., when the C or one of the |
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REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_PAGE_FAULT |
boolean |
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REPORT_VA_IN_VSTVAL_ON_LOAD_ACCESS_FAULT |
boolean |
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REPORT_VA_IN_VSTVAL_ON_LOAD_MISALIGNED |
boolean |
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REPORT_VA_IN_VSTVAL_ON_LOAD_PAGE_FAULT |
boolean |
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REPORT_VA_IN_VSTVAL_ON_STORE_AMO_ACCESS_FAULT |
boolean |
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REPORT_VA_IN_VSTVAL_ON_STORE_AMO_MISALIGNED |
boolean |
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REPORT_VA_IN_VSTVAL_ON_STORE_AMO_PAGE_FAULT |
boolean |
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SATP_MODE_BARE |
boolean |
Whether or not satp.MODE == Bare is supported. |
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SCOUNTENABLE_EN |
32-element array of boolean |
Indicates which counters can delegated via scounteren An unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false, it would be illegal to set SCOUNTENABLE_EN[3] to true. |
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STVAL_WIDTH |
≤ 0xffffffffffffffff |
The number of implemented bits in stval. Must be greater than or equal to max( |
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STVEC_MODE_DIRECT |
boolean |
Whether or not stvec.MODE supports Direct (0). |
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STVEC_MODE_VECTORED |
boolean |
Whether or not stvec.MODE supports Vectored (1). |
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SV32X4_TRANSLATION |
boolean |
Whether or not Sv32x4 translation mode is supported. |
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SV32_VSMODE_TRANSLATION |
boolean |
Whether or not Sv32 translation is supported in first-stage (VS-stage) translation. |
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SV39X4_TRANSLATION |
boolean |
Whether or not Sv39x4 translation mode is supported. |
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SV39_VSMODE_TRANSLATION |
boolean |
Whether or not Sv39 translation is supported in first-stage (VS-stage) translation. |
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SV48X4_TRANSLATION |
boolean |
Whether or not Sv48x4 translation mode is supported. |
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SV48_VSMODE_TRANSLATION |
boolean |
Whether or not Sv48 translation is supported in first-stage (VS-stage) translation. |
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SV57X4_TRANSLATION |
boolean |
Whether or not Sv57x4 translation mode is supported. |
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SV57_VSMODE_TRANSLATION |
boolean |
Whether or not Sv57 translation is supported in first-stage (VS-stage) translation. |
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SV_MODE_BARE |
boolean |
Whether or not writing mode=Bare is supported in the satp register. |
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SXLEN |
[32, 64, 3264] |
Set of XLENs supported in S-mode. Can be one of:
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S_MODE_ENDIANESS |
[little, big, dynamic] |
Endianess of data in S-mode. Can be one of:
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TIME_CSR_IMPLEMENTED |
boolean |
Whether or not a real hardware time CSR exists. Implementations can either provide a real CSR or emulate access at M-mode. Possible values:
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TINST_VALUE_ON_BREAKPOINT |
[always zero, custom] |
Value written into htinst/mtinst on a Breakpoint exception from VU/VS-mode. Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which resuls in UNPREDICTABLE |
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TINST_VALUE_ON_FINAL_INSTRUCTION_GUEST_PAGE_FAULT |
[always zero, always pseudoinstruction] |
Value to write into htval/mtval2 when there is a guest page fault on a final translation. Possible values: * "always zero": Always write the value zero * "always pseudoinstruction": Always write the pseudoinstruction |
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TINST_VALUE_ON_FINAL_LOAD_GUEST_PAGE_FAULT |
[always zero, always pseudoinstruction, always transformed standard instruction, custom] |
Value to write into htval/mtval2 when there is a guest page fault on a final translation. Possible values: * "always zero": Always write the value zero * "always pseudoinstruction": Always write the pseudoinstruction * "always transformed standard instruction": Always write the transformation of the standard instruction encoding * "custom": A custom value, which will cause an UNPREDICTABLE event. |
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TINST_VALUE_ON_FINAL_STORE_AMO_GUEST_PAGE_FAULT |
[always zero, always pseudoinstruction, always transformed standard instruction, custom] |
Value to write into htval/mtval2 when there is a guest page fault on a final translation. Possible values: * "always zero": Always write the value zero * "always pseudoinstruction": Always write the pseudoinstruction * "always transformed standard instruction": Always write the transformation of the standard instruction encoding * "custom": A custom value, which will cause an UNPREDICTABLE event. |
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TINST_VALUE_ON_INSTRUCTION_ADDRESS_MISALIGNED |
[always zero, custom] |
Value written into htinst/mtinst when there is an instruction address misaligned exception. Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which resuls in UNPREDICTABLE |
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TINST_VALUE_ON_LOAD_ACCESS_FAULT |
[always zero, always transformed standard instruction, custom] |
Value written into htinst/mtinst on an AccessFault exception from VU/VS-mode. Possible values: * "always zero": Always write the value zero * "always transformed standard instruction": Always write a transformed standard instruction as defined by H * "custom": Write a custom value, which resuls in UNPREDICTABLE |
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TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED |
[always zero, always transformed standard instruction, custom] |
Value written into htinst/mtinst on a VirtualInstruction exception from VU/VS-mode. Possible values: * "always zero": Always write the value zero * "always transformed standard instruction": Always write a transformed standard instruction as defined by H * "custom": Write a custom value, which resuls in UNPREDICTABLE |
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TINST_VALUE_ON_LOAD_PAGE_FAULT |
[always zero, always transformed standard instruction, custom] |
Value written into htinst/mtinst on a LoadPageFault exception from VU/VS-mode. Possible values: * "always zero": Always write the value zero * "always transformed standard instruction": Always write a transformed standard instruction as defined by H * "custom": Write a custom value, which resuls in UNPREDICTABLE |
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TINST_VALUE_ON_MCALL |
[always zero, custom] |
Value written into htinst/mtinst on a MCall exception from VU/VS-mode. Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which resuls in UNPREDICTABLE |
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TINST_VALUE_ON_SCALL |
[always zero, custom] |
Value written into htinst/mtinst on a SCall exception from VU/VS-mode. Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which resuls in UNPREDICTABLE |
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TINST_VALUE_ON_STORE_AMO_ACCESS_FAULT |
[always zero, always transformed standard instruction, custom] |
Value written into htinst/mtinst on an AccessFault exception from VU/VS-mode. Possible values: * "always zero": Always write the value zero * "always transformed standard instruction": Always write a transformed standard instruction as defined by H * "custom": Write a custom value, which resuls in UNPREDICTABLE |
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TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED |
[always zero, always transformed standard instruction, custom] |
Value written into htinst/mtinst on a VirtualInstruction exception from VU/VS-mode. Possible values: * "always zero": Always write the value zero * "always transformed standard instruction": Always write a transformed standard instruction as defined by H * "custom": Write a custom value, which resuls in UNPREDICTABLE |
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TINST_VALUE_ON_STORE_AMO_PAGE_FAULT |
[always zero, always transformed standard instruction, custom] |
Value written into htinst/mtinst on a StoreAmoPageFault exception from VU/VS-mode. Possible values: * "always zero": Always write the value zero * "always transformed standard instruction": Always write a transformed standard instruction as defined by H * "custom": Write a custom value, which resuls in UNPREDICTABLE |
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TINST_VALUE_ON_UCALL |
[always zero, custom] |
Value written into htinst/mtinst on a UCall exception from VU/VS-mode. Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which resuls in UNPREDICTABLE |
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TINST_VALUE_ON_VIRTUAL_INSTRUCTION |
[always zero, custom] |
Value written into htinst/mtinst on a VirtualInstruction exception from VU/VS-mode. Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which resuls in UNPREDICTABLE |
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TINST_VALUE_ON_VSCALL |
[always zero, custom] |
Value written into htinst/mtinst on a VSCall exception from VU/VS-mode. Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which resuls in UNPREDICTABLE |
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TRAP_ON_EBREAK |
boolean |
Whether or not an EBREAK causes a synchronous exception. The spec states that implementations may handle EBREAKs transparently without raising a trap, in which case the EEI must provide a builtin. |
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TRAP_ON_ECALL_FROM_M |
boolean |
Whether or not an ECALL-from-M-mode causes a synchronous exception. The spec states that implementations may handle ECALLs transparently without raising a trap, in which case the EEI must provide a builtin. |
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TRAP_ON_ECALL_FROM_S |
boolean |
Whether or not an ECALL-from-S-mode causes a synchronous exception. The spec states that implementations may handle ECALLs transparently without raising a trap, in which case the EEI must provide a builtin. |
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TRAP_ON_ECALL_FROM_U |
boolean |
Whether or not an ECALL-from-U-mode causes a synchronous exception. The spec states that implementations may handle ECALLs transparently without raising a trap, in which case the EEI must provide a builtin. |
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TRAP_ON_ECALL_FROM_VS |
boolean |
Whether or not an ECALL-from-VS-mode causes a synchronous exception. The spec states that implementations may handle ECALLs transparently without raising a trap, in which case the EEI must provide a builtin. |
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TRAP_ON_ILLEGAL_WLRL |
boolean |
When true, writing an illegal value to a WLRL CSR field raises an When false, writing an illegal value to a WLRL CSR field is |
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TRAP_ON_RESERVED_INSTRUCTION |
boolean |
When true, fetching an unimplemented and/or undefined instruction from the standard/reserved
encoding space will cause an When false, fetching such an instruction is |
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TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY |
boolean |
For implementations that make satp.MODE read-only zero (always Bare, i.e., no virtual translation is implemented), attempts to execute an SFENCE.VMA instruction might raise an illegal-instruction exception. TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY indicates whether or not that exception occurs. TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY has no effect when some virtual translation mode is supported. |
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TRAP_ON_UNIMPLEMENTED_CSR |
boolean |
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TRAP_ON_UNIMPLEMENTED_INSTRUCTION |
boolean |
When true, fetching an unimplemented instruction from the custom encoding space will cause
an When false, fetching an unimplemented instruction is |
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UXLEN |
[32, 64, 3264] |
Set of XLENs supported in U-mode. Can be one of:
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U_MODE_ENDIANESS |
[little, big, dynamic] |
Endianess of data in U-mode. Can be one of:
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VENDOR_ID_BANK |
25-bit integer |
JEDEC Vendor ID bank, for mvendorid |
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VENDOR_ID_OFFSET |
7-bit integer |
Vendor JEDEC code offset, for mvendorid |
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VMID_WIDTH |
0 to 14 |
Number of bits supported in hgatp.VMID (i.e., the supported width of a virtual machine ID). |
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VSXLEN |
[32, 64, 3264] |
Set of XLENs supported in VS-mode. Can be one of:
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VS_MODE_ENDIANESS |
[little, big, dynamic] |
Endianess of data in VS-mode. Can be one of:
|
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VUXLEN |
[32, 64, 3264] |
Set of XLENs supported in VU-mode. Can be one of:
|
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VU_MODE_ENDIANESS |
[little, big, dynamic] |
Endianess of data in VU-mode. Can be one of:
|
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XLEN |
[32, 64] |
XLEN in M-mode (AKA MXLEN, tracked by issue #52) |