Architectural Parameters

The following 144 parameters are defined in this manual:

Name Type Extension(s) Description

ARCH_ID

64-bit integer

Vendor-specific architecture ID in marchid

ASID_WIDTH

0 to 16

Number of implemented ASID bits. Maximum is 16 for XLEN==64, and 9 for XLEN==32

CONFIG_PTR_ADDRESS

integer

Physical address of the unified discovery configuration data structure. This address is reported in the mconfigptr CSR.

COUNTINHIBIT_EN

32-element array where:
  [0] is boolean
  [1] is false
  [2] is boolean
additional items are:
  boolean

Smhpm

Indicates which hardware performance monitor counters can be disabled from mcountinhibit.

An unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false, it would be illegal to set COUNTINHIBIT_EN[3] to true.

COUNTINHIBIT_EN[1] can never be true, since it corresponds to mcountinhibit, which is always read-only-0.

COUNTINHIBIT_EN[3:31] must all be false if Zihpm is not implemented.

GSTAGE_MODE_BARE

boolean

Whether or not writing mode=Bare is supported in the hgatp register.

HCOUNTENABLE_EN

32-element array of boolean

Indicates which counters can delegated via hcounteren

An unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false, it would be illegal to set HCOUNTENABLE_EN[3] to true.

HCOUNTENABLE_EN[0:2] must all be false if Zicntr is not implemented. HCOUNTENABLE_EN[3:31] must all be false if Zihpm is not implemented.

HPM_COUNTER_EN

32-element array where:
  [0] is false
  [1] is false
  [2] is false
additional items are:
  boolean

Smhpm

List of HPM counters that are enabled. There is one entry for each hpmcounter.

The first three entries must be false (as they correspond to CY, IR, TM in, e.g. mhmpcountinhibit) Index 3 in HPM_COUNTER_EN corresponds to hpmcounter3. Index 31 in HPM_COUNTER_EN corresponds to hpmcounter31.

HPM_EVENTS

array of 58-bit integer

Smhpm

List of defined event numbers that can be written into hpmeventN

HW_MSTATUS_FS_DIRTY_UPDATE

[never, precise, imprecise]

Indicates whether or not hardware will write to mstatus.FS

Values are:

never

Hardware never writes mstatus.FS

precise

Hardware writes mstatus.FS to the Dirty (3) state precisely when F registers are modified

imprecise

Hardware writes mstatus.FS imprecisely. This will result in a call to unpredictable() on any attempt to read mstatus or write FP state.

HW_MSTATUS_VS_DIRTY_UPDATE

[never, precise, imprecise]

Indicates whether or not hardware will write to mstatus.VS

Values are:

never

Hardware never writes mstatus.VS

precise

Hardware writes mstatus.VS to the Dirty (3) state precisely when V registers are modified

imprecise

Hardware writes mstatus.VS imprecisely. This will result in a call to unpredictable() on any attempt to read mstatus or write vector state.

IGNORE_INVALID_VSATP_MODE_WRITES_WHEN_V_EQ_ZERO

boolean

Whether writes from M-mode, U-mode, or S-mode to vsatp with an illegal mode setting are ignored (as they are with satp), or if they are treated as WARL, leading to undpredictable behavior.

IMP_ID

64-bit integer

Vendor-specific implementation ID in mimpid

LRSC_FAIL_ON_NON_EXACT_LRSC

boolean

Whether or not a Store Conditional fails if its physical address and size do not exactly match the physical address and size of the last Load Reserved in program order (independent of whether or not the SC is in the current reservation set)

LRSC_FAIL_ON_VA_SYNONYM

boolean

Whether or not an sc.l/sc.d will fail if its VA does not match the VA of the prior lr.l/lr.d, even if the physical address of the SC and LR are the same

LRSC_MISALIGNED_BEHAVIOR

[always raise misaligned exception, always raise access fault, custom]

What to do when an LR/SC address is misaligned and MISALIGNED_AMO == false.

'always raise misaligned exception': self-explainitory
'always raise access fault': self-explainitory
'custom': Custom behavior; misaligned LR/SC may sometimes raise a misaligned exception and sometimes raise a access fault. Will lead to an 'unpredictable' call on any misaligned LR/SC access

LRSC_RESERVATION_STRATEGY

[reserve naturally-aligned 64-byte region, reserve naturally-aligned 128-byte region, reserve exactly enough to cover the access, custom]

Strategy used to handle reservation sets.

"reserve naturally-aligned 64-byte region": Always reserve the 64-byte block containing the LR/SC address
"reserve naturally-aligned 128-byte region": Always reserve the 128-byte block containing the LR/SC address
"reserve exactly enough to cover the access": Always reserve exactly the LR/SC access, and no more
"custom": Custom behavior, leading to an 'unpredictable' call on any LR/SC

MCOUNTENABLE_EN

32-element array of boolean

Smhpm

Indicates which counters can be delegated via mcounteren.

An unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false, it would be illegal to set MCOUNTENABLE_EN[3] to true.

MCOUNTENABLE_EN[0:2] must all be false if Zicntr is not implemented. MCOUNTENABLE_EN[3:31] must all be false if Zihpm is not implemented.

MISALIGNED_AMO

boolean

whether or not the implementation supports misaligned atomics in main memory

MISALIGNED_LDST

boolean

Does the implementation perform non-atomic misaligned loads and stores to main memory (does not affect misaligned support to device memory)? If not, the implementation always throws a misaligned exception.

MISALIGNED_LDST_EXCEPTION_PRIORITY

[low, high]

The relative priority of a load/store/AMO exception vs. load/store/AMO page-fault or access-fault exceptions.

May be one of:

low

Misaligned load/store/AMO exceptions are always lower priority than load/store/AMO page-fault and access-fault exceptions.

high

Misaligned load/store/AMO exceptions are always higher priority than load/store/AMO page-fault and access-fault exceptions.

MISALIGNED_LDST_EXCEPTION_PRIORITY cannot be "high" when MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE is non-zero, since the atomicity of an access cannot be determined in that case until after address translation.

MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE

[0, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096]

The maximum granule size, in bytes, that the hart can atomically perform a misaligned load/store/AMO without raising a Misaligned exception. When MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE is 0, the hart cannot atomically perform a misaligned load/store/AMO. When a power of two, the hart can atomically load/store/AMO a misaligned access that is fully contained in a MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE-aligned region.

Even if the hart is capable of performing a misaligned load/store/AMO atomically, a misaligned exception may still occur if the access does not have the appropriate Misaligned Atomicity Granule PMA set.

MISALIGNED_SPLIT_STRATEGY

[by_byte, custom]

When misaligned accesses are supported, this determines the order in the implementation appears to process the load/store, which determines how/which exceptions will be reported

Options:

by_byte: The load/store appears to be broken into byte-sized accesses that processed sequentially from smallest address to largest address
custom: Something else. Will result in a call to unpredictable() in the execution

MISA_CSR_IMPLEMENTED

boolean

Whether or not the misa CSR returns zero or a non-zero value.

Possible values:

true: The misa CSR returns a non-zero value.
false: The misa CSR is read-only-0.

MSTATUS_FS_LEGAL_VALUES

at most 4-element array of [0, 1, 2, 3]

F, S

The set of values that mstatus.FS will accept from a software write.

MSTATUS_FS_WRITEABLE

boolean

When S is enabled but F is not, mstatus.FS is optionally writeable.

This parameter only has an effect when both S and F mode are disabled.

MSTATUS_TVM_IMPLEMENTED

boolean

Whether or not mstatus.TVM is implemented.

When not implemented mstatus.TVM will be read-only-zero.

MSTATUS_VS_LEGAL_VALUES

at most 4-element array of [0, 1, 2, 3]

V, S

The set of values that mstatus.VS will accept from a software write.

MSTATUS_VS_WRITEABLE

boolean

When S is enabled but V is not, mstatus.VS is optionally writeable.

This parameter only has an effect when both S and V mode are disabled.

MTVAL_WIDTH

≤ 64

The number of implemented bits in the mtval CSR. This is the CSR that may be written when a trap is taken into M-mode with exception-specific information to assist software in handling the trap (e.g., address associated with exception).

Must be greater than or equal to max(PHYS_ADDR_WIDTH, VA_SIZE)

MTVEC_BASE_ALIGNMENT_DIRECT

≥ 4

Byte alignment for mtvec.BASE when mtvec.MODE is Direct.

Cannot be less than 4-byte alignment.

MTVEC_BASE_ALIGNMENT_VECTORED

≥ 4

Byte alignment for mtvec.BASE when mtvec.MODE is Vectored.

Cannot be less than 4-byte alignment.

MTVEC_MODES

1-element to 2-element array of [0, 1]

Modes supported by mtvec.MODE. If only one, it is assumed to be read-only with that value.

MUTABLE_MISA_A

boolean

When the A extensions is supported, indicates whether or not the extension can be disabled in the misa.A bit.

MUTABLE_MISA_B

boolean

Indicates whether or not the B extension can be disabled with the misa.B bit.

MUTABLE_MISA_D

boolean

Indicates whether or not the D extension can be disabled with the misa.D bit.

MUTABLE_MISA_F

boolean

Indicates whether or not the F extension can be disabled with the misa.F bit.

MUTABLE_MISA_H

boolean

Indicates whether or not the H extension can be disabled with the misa.H bit.

MUTABLE_MISA_M

boolean

Indicates whether or not the M extension can be disabled with the misa.M bit.

MUTABLE_MISA_S

boolean

Indicates whether or not the S extension can be disabled with the misa.S bit.

MUTABLE_MISA_U

boolean

Indicates whether or not the U extension can be disabled with the misa.U bit.

MUTABLE_MISA_V

boolean

Indicates whether or not the V extension can be disabled with the misa.V bit.

M_MODE_ENDIANESS

[little, big, dynamic]

Endianess of data in M-mode. Can be one of:

little

M-mode data is always little endian

big

M-mode data is always big endian

dynamic

M-mode data can be either little or big endian, depending on the CSR field mstatus.MBE

NUM_EXTERNAL_GUEST_INTERRUPTS

1 to 63

Number of supported virtualized guest interrupts

Corresponds to the GEILEN parameter in the RVI specs

NUM_PMP_ENTRIES

0 to 64

Smpmp

Number of implemented PMP entries. Can be any value between 0-64, inclusive.

The architecture mandates that the number of implemented PMP registers must appear to be 0, 16, or 64.

Therefore, pmp registers will behave as follows according to NUN_PMP_ENTRIES:

NUM_PMP_ENTRIES

pmpaddr<0-15> / pmpcfg<0-3>

pmpaddr<16-63> / pmpcfg<4-15>

1-16

17-64

N = Not implemented; access will cause IllegalInstruction if TRAP_ON_UNIMPLEMENTED_CSR is true
Y = Implemented; access will not cause an exception (from M-mode), but register may be read-only-zero if NUM_PMP_ENTRIES is less than the corresponding register

pmpcfgN for an odd N never exists when XLEN == 64

When NUM_PMP_ENTRIES is not exactly 0, 16, or 64, some extant pmp registers, and associated pmpNcfg, will be read-only zero (but will never cause an exception).

PHYS_ADDR_WIDTH

≤ 64

Number of bits in the physical address space.

PMA_GRANULARITY

2 to 66

log2 of the smallest supported PMA region.

Generally, for systems with an MMU, should not be smaller than 12, as that would preclude caching PMP results in the TLB along with virtual memory translations

PMP_GRANULARITY

2 to 66

Smpmp

log2 of the smallest supported PMP region.

Generally, for systems with an MMU, should not be smaller than 12, as that would preclude caching PMP results in the TLB along with virtual memory translations

Note that PMP_GRANULARITY is equal to G+2 (not G) as described in the privileged architecture.

PRECISE_SYNCHRONOUS_EXCEPTIONS

boolean

Whether or not all synchronous exceptions are precise.

If false, any exception not otherwise mandated to precise (e.g., PMP violation) will cause execution to enter an unpredictable state.

REPORT_CAUSE_IN_MTVAL_ON_LANDING_PAD_SOFTWARE_CHECK

boolean

Zicfilp

When true, mtval is written with the shadow stack casue (code=18) when a SoftwareCheck exception is raised into M-mode due to a landing pad error.

When false, mtval is written with 0.

REPORT_CAUSE_IN_MTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK

boolean

Zicfiss

When true, mtval is written with the shadow stack casue (code=3) when a SoftwareCheck exception is raised into M-mode due to a shadow stack pop check instruction.

When false, mtval is written with 0.

REPORT_CAUSE_IN_STVAL_ON_LANDING_PAD_SOFTWARE_CHECK

boolean

Zicfilp

When true, stval is written with the shadow stack casue (code=18) when a SoftwareCheck exception is raised into S-mode due to a landing pad error.

When false, stval is written with 0.

REPORT_CAUSE_IN_STVAL_ON_SHADOW_STACK_SOFTWARE_CHECK

boolean

Zicfiss

When true, stval is written with the shadow stack casue (code=3) when a SoftwareCheck exception is raised into S-mode due to a shadow stack pop check instruction.

When false, stval is written with 0.

REPORT_CAUSE_IN_VSTVAL_ON_LANDING_PAD_SOFTWARE_CHECK

boolean

Zicfilp

When true, vstval is written with the shadow stack casue (code=18) when a SoftwareCheck exception is raised into VS-mode due to a landing pad error.

When false, vstval is written with 0.

REPORT_CAUSE_IN_VSTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK

boolean

Zicfiss

When true, vstval is written with the shadow stack casue (code=3) when a SoftwareCheck exception is raised into VS-mode due to a shadow stack pop check instruction.

When false, vstval is written with 0.

REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION

boolean

When true, mtval is written with the encoding of an instruction that causes an IllegalInstruction exception.

When false mtval is written with 0 when an IllegalInstruction exception occurs.

REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION

boolean

When true, stval is written with the encoding of an instruction that causes an IllegalInstruction exception.

When false stval is written with 0 when an IllegalInstruction exception occurs.

REPORT_ENCODING_IN_VSTVAL_ON_ILLEGAL_INSTRUCTION

boolean

When true, vstval is written with the encoding of an instruction that causes an IllegalInstruction exception.

When false vstval is written with 0 when an IllegalInstruction exception occurs.

REPORT_GPA_IN_TVAL_ON_INSTRUCTION_GUEST_PAGE_FAULT

boolean

Whether or not GPA >> 2 is written into htval/mtval2 when an instruction guest page fault occurs.

If false, 0 will be written into htval/mtval2 on an instruction guest page fault.

REPORT_GPA_IN_TVAL_ON_INTERMEDIATE_GUEST_PAGE_FAULT

boolean

Whether or not GPA >> 2 is written into htval/mtval2 when a guest page fault occurs while walking a VS-mode page table.

If false, 0 will be written into htval/mtval2 on an intermediate guest page fault.

REPORT_GPA_IN_TVAL_ON_LOAD_GUEST_PAGE_FAULT

boolean

Whether or not GPA >> 2 is written into htval/mtval2 when a load guest page fault occurs.

If false, 0 will be written into htval/mtval2 on a load guest page fault.

REPORT_GPA_IN_TVAL_ON_STORE_AMO_GUEST_PAGE_FAULT

boolean

Whether or not GPA >> 2 is written into htval/mtval2 when a store/amo guest page fault occurs.

If false, 0 will be written into htval/mtval2 on a store/amo guest page fault.

REPORT_VA_IN_MTVAL_ON_BREAKPOINT

boolean

When true, mtval is written with the virtual PC of the EBREAK instruction (same information as mepc).

When false, mtval is written with 0 on an EBREAK instruction.

Regardless, mtval is always written with a virtual PC when an external breakpoint is generated

REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT

boolean

When true, mtval is written with the virtual PC of an instructino when fetch causes an InstructionAccessFault.

WHen false, mtval is written with 0 when an instruction fetch causes an InstructionAccessFault.

REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED

boolean

When true, mtval is written with the virtual PC when an instruction fetch is misaligned.

When false, mtval is written with 0 when an instruction fetch is misaligned.

Note that when IALIGN=16 (i.e., when the C or one of the Zc* extensions are implemented), it is impossible to generate a misaligned fetch, and so this parameter has no effect.

REPORT_VA_IN_MTVAL_ON_INSTRUCTION_PAGE_FAULT

boolean

When true, mtval is written with the virtual PC of an instructino when fetch causes an InstructionPageFault.

WHen false, mtval is written with 0 when an instruction fetch causes an InstructionPageFault.

REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT

boolean

When true, mtval is written with the virtual address of a load when it causes a LoadAccessFault.

WHen false, mtval is written with 0 when a load causes a LoadAccessFault.

REPORT_VA_IN_MTVAL_ON_LOAD_MISALIGNED

boolean

When true, mtval is written with the virtual address of a load instruction when the address is misaligned and MISALIGNED_LDST is false.

When false, mtval is written with 0 when a load address is misaligned and MISALIGNED_LDST is false.

REPORT_VA_IN_MTVAL_ON_LOAD_PAGE_FAULT

boolean

When true, mtval is written with the virtual address of a load when it causes a LoadPageFault.

WHen false, mtval is written with 0 when a load causes a LoadPageFault.

REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT

boolean

When true, mtval is written with the virtual address of a store when it causes a StoreAmoAccessFault.

WHen false, mtval is written with 0 when a store causes a StoreAmoAccessFault.

REPORT_VA_IN_MTVAL_ON_STORE_AMO_MISALIGNED

boolean

When true, mtval is written with the virtual address of a store instruction when the address is misaligned and MISALIGNED_LDST is false.

When false, mtval is written with 0 when a store address is misaligned and MISALIGNED_LDST is false.

REPORT_VA_IN_MTVAL_ON_STORE_AMO_PAGE_FAULT

boolean

When true, mtval is written with the virtual address of a store when it causes a StoreAmoPageFault.

WHen false, mtval is written with 0 when a store causes a StoreAmoPageFault.

REPORT_VA_IN_STVAL_ON_BREAKPOINT

boolean

When true, stval is written with the virtual PC of the EBREAK instruction (same information as mepc).

When false, stval is written with 0 on an EBREAK instruction.

Regardless, stval is always written with a virtual PC when an external breakpoint is generated

REPORT_VA_IN_STVAL_ON_INSTRUCTION_ACCESS_FAULT

boolean

When true, stval is written with the virtual PC of an instructino when fetch causes an InstructionAccessFault.

WHen false, stval is written with 0 when an instruction fetch causes an InstructionAccessFault.

REPORT_VA_IN_STVAL_ON_INSTRUCTION_MISALIGNED

boolean

When true, stval is written with the virtual PC when an instruction fetch is misaligned.

When false, stval is written with 0 when an instruction fetch is misaligned.

Note that when IALIGN=16 (i.e., when the C or one of the Zc* extensions are implemented), it is impossible to generate a misaligned fetch, and so this parameter has no effect.

REPORT_VA_IN_STVAL_ON_INSTRUCTION_PAGE_FAULT

boolean

When true, stval is written with the virtual PC of an instructino when fetch causes an InstructionPageFault.

WHen false, stval is written with 0 when an instruction fetch causes an InstructionPageFault.

REPORT_VA_IN_STVAL_ON_LOAD_ACCESS_FAULT

boolean

When true, stval is written with the virtual address of a load when it causes a LoadAccessFault.

WHen false, stval is written with 0 when a load causes a LoadAccessFault.

REPORT_VA_IN_STVAL_ON_LOAD_MISALIGNED

boolean

When true, stval is written with the virtual address of a load instruction when the address is misaligned and MISALIGNED_LDST is false.

When false, stval is written with 0 when a load address is misaligned and MISALIGNED_LDST is false.

REPORT_VA_IN_STVAL_ON_LOAD_PAGE_FAULT

boolean

When true, stval is written with the virtual address of a load when it causes a LoadPageFault.

WHen false, stval is written with 0 when a load causes a LoadPageFault.

REPORT_VA_IN_STVAL_ON_STORE_AMO_ACCESS_FAULT

boolean

When true, stval is written with the virtual address of a store when it causes a StoreAmoAccessFault.

WHen false, stval is written with 0 when a store causes a StoreAmoAccessFault.

REPORT_VA_IN_STVAL_ON_STORE_AMO_MISALIGNED

boolean

When true, stval is written with the virtual address of a store instruction when the address is misaligned and MISALIGNED_LDST is false.

When false, stval is written with 0 when a store address is misaligned and MISALIGNED_LDST is false.

REPORT_VA_IN_STVAL_ON_STORE_AMO_PAGE_FAULT

boolean

When true, stval is written with the virtual address of a store when it causes a StoreAmoPageFault.

WHen false, stval is written with 0 when a store causes a StoreAmoPageFault.

REPORT_VA_IN_VSTVAL_ON_BREAKPOINT

boolean

When true, vstval is written with the virtual PC of the EBREAK instruction (same information as mepc).

When false, vstval is written with 0 on an EBREAK instruction.

Regardless, vstval is always written with a virtual PC when an external breakpoint is generated

REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_ACCESS_FAULT

boolean

When true, vstval is written with the virtual PC of an instructino when fetch causes an InstructionAccessFault.

WHen false, vstval is written with 0 when an instruction fetch causes an InstructionAccessFault.

REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_MISALIGNED

boolean

When true, vstval is written with the virtual PC when an instruction fetch is misaligned.

When false, vstval is written with 0 when an instruction fetch is misaligned.

Note that when IALIGN=16 (i.e., when the C or one of the Zc* extensions are implemented), it is impossible to generate a misaligned fetch, and so this parameter has no effect.

REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_PAGE_FAULT

boolean

When true, vstval is written with the virtual PC of an instructino when fetch causes an InstructionPageFault.

WHen false, vstval is written with 0 when an instruction fetch causes an InstructionPageFault.

REPORT_VA_IN_VSTVAL_ON_LOAD_ACCESS_FAULT

boolean

When true, vstval is written with the virtual address of a load when it causes a LoadAccessFault.

WHen false, vstval is written with 0 when a load causes a LoadAccessFault.

REPORT_VA_IN_VSTVAL_ON_LOAD_MISALIGNED

boolean

When true, vstval is written with the virtual address of a load instruction when the address is misaligned and MISALIGNED_LDST is false.

When false, vstval is written with 0 when a load address is misaligned and MISALIGNED_LDST is false.

REPORT_VA_IN_VSTVAL_ON_LOAD_PAGE_FAULT

boolean

When true, vstval is written with the virtual address of a load when it causes a LoadPageFault.

WHen false, vstval is written with 0 when a load causes a LoadPageFault.

REPORT_VA_IN_VSTVAL_ON_STORE_AMO_ACCESS_FAULT

boolean

When true, vstval is written with the virtual address of a store when it causes a StoreAmoAccessFault.

WHen false, vstval is written with 0 when a store causes a StoreAmoAccessFault.

REPORT_VA_IN_VSTVAL_ON_STORE_AMO_MISALIGNED

boolean

When true, vstval is written with the virtual address of a store instruction when the address is misaligned and MISALIGNED_LDST is false.

When false, vstval is written with 0 when a store address is misaligned and MISALIGNED_LDST is false.

REPORT_VA_IN_VSTVAL_ON_STORE_AMO_PAGE_FAULT

boolean

When true, vstval is written with the virtual address of a store when it causes a StoreAmoPageFault.

WHen false, vstval is written with 0 when a store causes a StoreAmoPageFault.

SATP_MODE_BARE

boolean

Whether or not satp.MODE == Bare is supported.

SCOUNTENABLE_EN

32-element array of boolean

Indicates which counters can delegated via scounteren

An unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false, it would be illegal to set SCOUNTENABLE_EN[3] to true.

SCOUNTENABLE_EN[0:2] must all be false if Zicntr is not implemented. SCOUNTENABLE_EN[3:31] must all be false if Zihpm is not implemented.

STVAL_WIDTH

≤ 0xffffffffffffffff

The number of implemented bits in stval.

Must be greater than or equal to max(PHYS_ADDR_WIDTH, VA_SIZE)

STVEC_MODE_DIRECT

boolean

Whether or not stvec.MODE supports Direct (0).

STVEC_MODE_VECTORED

boolean

Whether or not stvec.MODE supports Vectored (1).

SV32X4_TRANSLATION

boolean

Whether or not Sv32x4 translation mode is supported.

SV32_VSMODE_TRANSLATION

boolean

Whether or not Sv32 translation is supported in first-stage (VS-stage) translation.

SV39X4_TRANSLATION

boolean

Whether or not Sv39x4 translation mode is supported.

SV39_VSMODE_TRANSLATION

boolean

Whether or not Sv39 translation is supported in first-stage (VS-stage) translation.

SV48X4_TRANSLATION

boolean

Whether or not Sv48x4 translation mode is supported.

SV48_VSMODE_TRANSLATION

boolean

Whether or not Sv48 translation is supported in first-stage (VS-stage) translation.

SV57X4_TRANSLATION

boolean

Whether or not Sv57x4 translation mode is supported.

SV57_VSMODE_TRANSLATION

boolean

Whether or not Sv57 translation is supported in first-stage (VS-stage) translation.

SV_MODE_BARE

boolean

Whether or not writing mode=Bare is supported in the satp register.

SXLEN

[32, 64, 3264]

Set of XLENs supported in S-mode. Can be one of:

32: SXLEN is always 32
64: SXLEN is always 64
3264: SXLEN can be changed (via mstatus.SXL) between 32 and 64

S_MODE_ENDIANESS

[little, big, dynamic]

Endianess of data in S-mode. Can be one of:

little: M-mode data is always little endian
big: M-mode data is always big endian
dynamic: M-mode data can be either little or big endian, depending on the CSR field mstatus.SBE

TIME_CSR_IMPLEMENTED

boolean

Zicntr

Whether or not a real hardware time CSR exists. Implementations can either provide a real CSR or emulate access at M-mode.

Possible values:

true: time/timeh exists, and accessing it will not cause an IllegalInstruction trap
false: time/timeh does not exist. Accessing the CSR will cause an IllegalInstruction trap or enter an unpredictable state, depending on TRAP_ON_UNIMPLEMENTED_CSR. Privileged software may emulate the time CSR, or may pass the exception to a lower level.

TINST_VALUE_ON_BREAKPOINT

[always zero, custom]

Value written into htinst/mtinst on a Breakpoint exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which resuls in UNPREDICTABLE

TINST_VALUE_ON_FINAL_INSTRUCTION_GUEST_PAGE_FAULT

[always zero, always pseudoinstruction]

Value to write into htval/mtval2 when there is a guest page fault on a final translation.

Possible values: * "always zero": Always write the value zero * "always pseudoinstruction": Always write the pseudoinstruction

TINST_VALUE_ON_FINAL_LOAD_GUEST_PAGE_FAULT

[always zero, always pseudoinstruction, always transformed standard instruction, custom]

Value to write into htval/mtval2 when there is a guest page fault on a final translation.

Possible values: * "always zero": Always write the value zero * "always pseudoinstruction": Always write the pseudoinstruction * "always transformed standard instruction": Always write the transformation of the standard instruction encoding * "custom": A custom value, which will cause an UNPREDICTABLE event.

TINST_VALUE_ON_FINAL_STORE_AMO_GUEST_PAGE_FAULT

[always zero, always pseudoinstruction, always transformed standard instruction, custom]

Value to write into htval/mtval2 when there is a guest page fault on a final translation.

TINST_VALUE_ON_INSTRUCTION_ADDRESS_MISALIGNED

[always zero, custom]

Value written into htinst/mtinst when there is an instruction address misaligned exception.

Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which resuls in UNPREDICTABLE

TINST_VALUE_ON_LOAD_ACCESS_FAULT

[always zero, always transformed standard instruction, custom]

Value written into htinst/mtinst on an AccessFault exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "always transformed standard instruction": Always write a transformed standard instruction as defined by H * "custom": Write a custom value, which resuls in UNPREDICTABLE

TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED

[always zero, always transformed standard instruction, custom]

Value written into htinst/mtinst on a VirtualInstruction exception from VU/VS-mode.

TINST_VALUE_ON_LOAD_PAGE_FAULT

[always zero, always transformed standard instruction, custom]

Value written into htinst/mtinst on a LoadPageFault exception from VU/VS-mode.

TINST_VALUE_ON_MCALL

[always zero, custom]

Value written into htinst/mtinst on a MCall exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which resuls in UNPREDICTABLE

TINST_VALUE_ON_SCALL

[always zero, custom]

Value written into htinst/mtinst on a SCall exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which resuls in UNPREDICTABLE

TINST_VALUE_ON_STORE_AMO_ACCESS_FAULT

[always zero, always transformed standard instruction, custom]

Value written into htinst/mtinst on an AccessFault exception from VU/VS-mode.

TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED

[always zero, always transformed standard instruction, custom]

Value written into htinst/mtinst on a VirtualInstruction exception from VU/VS-mode.

TINST_VALUE_ON_STORE_AMO_PAGE_FAULT

[always zero, always transformed standard instruction, custom]

Value written into htinst/mtinst on a StoreAmoPageFault exception from VU/VS-mode.

TINST_VALUE_ON_UCALL

[always zero, custom]

Value written into htinst/mtinst on a UCall exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which resuls in UNPREDICTABLE

TINST_VALUE_ON_VIRTUAL_INSTRUCTION

[always zero, custom]

Value written into htinst/mtinst on a VirtualInstruction exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which resuls in UNPREDICTABLE

TINST_VALUE_ON_VSCALL

[always zero, custom]

Value written into htinst/mtinst on a VSCall exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which resuls in UNPREDICTABLE

TRAP_ON_EBREAK

boolean

Whether or not an EBREAK causes a synchronous exception.

The spec states that implementations may handle EBREAKs transparently without raising a trap, in which case the EEI must provide a builtin.

TRAP_ON_ECALL_FROM_M

boolean

Whether or not an ECALL-from-M-mode causes a synchronous exception.

The spec states that implementations may handle ECALLs transparently without raising a trap, in which case the EEI must provide a builtin.

TRAP_ON_ECALL_FROM_S

boolean

Whether or not an ECALL-from-S-mode causes a synchronous exception.

The spec states that implementations may handle ECALLs transparently without raising a trap, in which case the EEI must provide a builtin.

TRAP_ON_ECALL_FROM_U

boolean

Whether or not an ECALL-from-U-mode causes a synchronous exception.

The spec states that implementations may handle ECALLs transparently without raising a trap, in which case the EEI must provide a builtin.

TRAP_ON_ECALL_FROM_VS

boolean

Whether or not an ECALL-from-VS-mode causes a synchronous exception.

The spec states that implementations may handle ECALLs transparently without raising a trap, in which case the EEI must provide a builtin.

TRAP_ON_ILLEGAL_WLRL

boolean

When true, writing an illegal value to a WLRL CSR field raises an IllegalInstruction exception.

When false, writing an illegal value to a WLRL CSR field is unpredictable.

TRAP_ON_RESERVED_INSTRUCTION

boolean

When true, fetching an unimplemented and/or undefined instruction from the standard/reserved encoding space will cause an IllegalInstruction exception.

When false, fetching such an instruction is UNPREDICTABLE.

TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY

boolean

For implementations that make satp.MODE read-only zero (always Bare, i.e., no virtual translation is implemented), attempts to execute an SFENCE.VMA instruction might raise an illegal-instruction exception.

TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY indicates whether or not that exception occurs.

TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY has no effect when some virtual translation mode is supported.

TRAP_ON_UNIMPLEMENTED_CSR

boolean

When true, accessing an unimplemented CSR (via a Zicsr instruction) will cause an IllegalInstruction exception.

When false, accessing an unimplemented CSR (via a Zicsr instruction) is unpredictable.

TRAP_ON_UNIMPLEMENTED_INSTRUCTION

boolean

When true, fetching an unimplemented instruction from the custom encoding space will cause an IllegalInstruction exception.

When false, fetching an unimplemented instruction is UNPREDICTABLE.

UXLEN

[32, 64, 3264]

Set of XLENs supported in U-mode. Can be one of:

32: SXLEN is always 32
64: SXLEN is always 64
3264: SXLEN can be changed (via mstatus.UXL) between 32 and 64

U_MODE_ENDIANESS

[little, big, dynamic]

Endianess of data in U-mode. Can be one of:

little: M-mode data is always little endian
big: M-mode data is always big endian
dynamic: M-mode data can be either little or big endian, depending on the CSR field mstatus.UBE

VENDOR_ID_BANK

25-bit integer

JEDEC Vendor ID bank, for mvendorid

VENDOR_ID_OFFSET

7-bit integer

Vendor JEDEC code offset, for mvendorid

VMID_WIDTH

0 to 14

Number of bits supported in hgatp.VMID (i.e., the supported width of a virtual machine ID).

VSXLEN

[32, 64, 3264]

Set of XLENs supported in VS-mode. Can be one of:

32: VSXLEN is always 32
64: VSXLEN is always 64
3264: VSXLEN can be changed (via hstatus.VSXL) between 32 and 64

VS_MODE_ENDIANESS

[little, big, dynamic]

Endianess of data in VS-mode. Can be one of:

little: M-mode data is always little endian
big: M-mode data is always big endian
dynamic: M-mode data can be either little or big endian, depending on the CSR field hstatus.VSBE

VUXLEN

[32, 64, 3264]

Set of XLENs supported in VU-mode. Can be one of:

32: VUXLEN is always 32
64: VUXLEN is always 64
3264: VUXLEN can be changed (via vsstatus.UXL) between 32 and 64

VU_MODE_ENDIANESS

[little, big, dynamic]

Endianess of data in VU-mode. Can be one of:

little: M-mode data is always little endian
big: M-mode data is always big endian
dynamic: M-mode data can be either little or big endian, depending on the CSR field vsstatus.UBE

XLEN

[32, 64]

XLEN in M-mode (AKA MXLEN, tracked by issue #52)