rorw

Rotate right word (Register)

This instruction is defined by:

anyOf:
- B, version >= 0
- Zbb, version >= 0
- Zbkb, version >= 0
- Zk, version >= 0
- Zkn, version >= 0
- Zks, version >= 0

This instruction is included in the following profiles:

RVA22U64 (Mandatory)

Encoding

Assembly format

rorw rd, rs1, rs2

Synopsis

This instruction must have data-independent timing when extension Zkt is enabled.

This instruction performs a rotate right on the least-significant word of rs1 by the amount in least-significant 5 bits of rs2. The resultant word is sign-extended by copying bit 31 to all of the more-significant bits.

Access

M	HS	U	VS	VU
Always	Always	Always	Always	Always

Always

Decode Variables

Bits<5> shamt = $encoding[24:20];
Bits<5> rs1 = $encoding[19:15];
Bits<5> rd = $encoding[11:7];

Execution

IDL
Sail

if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
  raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
}
XReg rs1_word = X[rs1][31:0];
XReg shamt = X[rs1][4:0];
XReg unextended_result = (X[rs1] >> shamt) | (X[rs1] << (32 - shamt));
X[rd] = {{32{unextended_result[31]}}, unextended_result};

{
  let rs1_val = (X(rs1))[31..0];
  let shamt = (X(rs2))[4..0];
  let result : bits(32) = match op {
    RISCV_ROLW => rs1_val <<< shamt,
    RISCV_RORW => rs1_val >>> shamt
  };
  X(rd) = sign_extend(result);
  RETIRE_SUCCESS
}

Exceptions

This instruction may result in the following synchronous exceptions:

IllegalInstruction