pmpcfg14

PMP Configuration Register 14

PMP entry configuration

Attributes

Defining Extension

  • Smpmp, version >= 0

CSR Address

0x3ae

Length

32-bit

64-bit

Privilege Mode

M

Format

This CSR format changes dynamically.

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Field Summary

Name Location Type Reset Value

pmp56cfg

7:0

RW-R
RO
UNDEFINED_LEGAL
0

pmp57cfg

15:8

RW-R
RO
UNDEFINED_LEGAL
0

pmp58cfg

23:16

RW-R
RO
UNDEFINED_LEGAL
0

pmp59cfg

31:24

RW-R
RO
UNDEFINED_LEGAL
0

pmp60cfg

39:32

RW-R
RO
UNDEFINED_LEGAL
0

pmp61cfg

47:40

RW-R
RO
UNDEFINED_LEGAL
0

pmp62cfg

55:48

RW-R
RO
UNDEFINED_LEGAL
0

pmp63cfg

63:56

RW-R
RO
UNDEFINED_LEGAL
0

Fields

pmp56cfg

Location

7:0

Description

PMP configuration for entry 56

The bits are as follows:

[separator="!",%autowidth]
!===
! Name ! Location ! Description

h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
h! - ! 6:5 ! Reserved Writes shall be ignored.
h! A ! 4:3
a! Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]

  • OFF (0) - Null region (disabled)

  • TOR (1) - Top of range

  • NA4 (2) - Naturally aligned four-byte region

  • NAPOT (3) - Natrually aligned power of two
    + [when="PMP_GRANULARITY >= 2"]

  • OFF (0) - Null region (disabled)

  • TOR (1) - Top of range

  • NAPOT (3) - Natrually aligned power of two

    [when="PMP_GRANULARITY >= 2"]
    Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

    h! X ! 2 ! When clear, instruction fetchs cause an Access Fault for the matching region and privilege mode.
    h! W ! 1 ! When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.
    h! R ! 0 ! When clear, loads cause an Access Fault for the matching region and privilege mode.
    !===

    The combination of R = 0, W = 1 is reserved.

Type
RW-R
RO
Reset value
UNDEFINED_LEGAL
0

pmp57cfg

Location

15:8

Description

PMP configuration for entry 57

The bits are as follows:

[separator="!",%autowidth]
!===
! Name ! Location ! Description

h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
h! - ! 14:13 ! Reserved Writes shall be ignored.
h! A ! 12:11
a! Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]

  • OFF (0) - Null region (disabled)

  • TOR (1) - Top of range

  • NA4 (2) - Naturally aligned four-byte region

  • NAPOT (3) - Natrually aligned power of two
    + [when="PMP_GRANULARITY >= 2"]

  • OFF (0) - Null region (disabled)

  • TOR (1) - Top of range

  • NAPOT (3) - Natrually aligned power of two

    [when="PMP_GRANULARITY >= 2"]
    Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

    h! X ! 10 ! When clear, instruction fetchs cause an Access Fault for the matching region and privilege mode.
    h! W ! 9 ! When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.
    h! R ! 8 ! When clear, loads cause an Access Fault for the matching region and privilege mode.
    !===

    The combination of R = 0, W = 1 is reserved.

Type
RW-R
RO
Reset value
UNDEFINED_LEGAL
0

pmp58cfg

Location

23:16

Description

PMP configuration for entry 58

The bits are as follows:

[separator="!",%autowidth]
!===
! Name ! Location ! Description

h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
h! - ! 22:21 ! Reserved Writes shall be ignored.
h! A ! 20:19
a! Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]

  • OFF (0) - Null region (disabled)

  • TOR (1) - Top of range

  • NA4 (2) - Naturally aligned four-byte region

  • NAPOT (3) - Natrually aligned power of two
    + [when="PMP_GRANULARITY >= 2"]

  • OFF (0) - Null region (disabled)

  • TOR (1) - Top of range

  • NAPOT (3) - Natrually aligned power of two

    [when="PMP_GRANULARITY >= 2"]
    Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

    h! X ! 18 ! When clear, instruction fetchs cause an Access Fault for the matching region and privilege mode.
    h! W ! 17 ! When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.
    h! R ! 16 ! When clear, loads cause an Access Fault for the matching region and privilege mode.
    !===

    The combination of R = 0, W = 1 is reserved.

Type
RW-R
RO
Reset value
UNDEFINED_LEGAL
0

pmp59cfg

Location

31:24

Description

PMP configuration for entry 59

The bits are as follows:

[separator="!",%autowidth]
!===
! Name ! Location ! Description

h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
h! - ! 30:29 ! Reserved Writes shall be ignored.
h! A ! 28:27
a! Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]

  • OFF (0) - Null region (disabled)

  • TOR (1) - Top of range

  • NA4 (2) - Naturally aligned four-byte region

  • NAPOT (3) - Natrually aligned power of two
    + [when="PMP_GRANULARITY >= 2"]

  • OFF (0) - Null region (disabled)

  • TOR (1) - Top of range

  • NAPOT (3) - Natrually aligned power of two

    [when="PMP_GRANULARITY >= 2"]
    Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

    h! X ! 26 ! When clear, instruction fetchs cause an Access Fault for the matching region and privilege mode.
    h! W ! 25 ! When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.
    h! R ! 24 ! When clear, loads cause an Access Fault for the matching region and privilege mode.
    !===

    The combination of R = 0, W = 1 is reserved.

Type
RW-R
RO
Reset value
UNDEFINED_LEGAL
0

pmp60cfg

pmp60cfg is only defined in RV64 (CSR[misa].MXL == 1)
Location

39:32

Description

PMP configuration for entry 60

The bits are as follows:

[separator="!",%autowidth]
!===
! Name ! Location ! Description

h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
h! - ! 38:37 ! Reserved Writes shall be ignored.
h! A ! 36:35
a! Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]

  • OFF (0) - Null region (disabled)

  • TOR (1) - Top of range

  • NA4 (2) - Naturally aligned four-byte region

  • NAPOT (3) - Natrually aligned power of two
    + [when="PMP_GRANULARITY >= 2"]

  • OFF (0) - Null region (disabled)

  • TOR (1) - Top of range

  • NAPOT (3) - Natrually aligned power of two

    [when="PMP_GRANULARITY >= 2"]
    Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

    h! X ! 34 ! When clear, instruction fetchs cause an Access Fault for the matching region and privilege mode.
    h! W ! 33 ! When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.
    h! R ! 32 ! When clear, loads cause an Access Fault for the matching region and privilege mode.
    !===

    The combination of R = 0, W = 1 is reserved.

Type
RW-R
RO
Reset value
UNDEFINED_LEGAL
0

pmp61cfg

pmp61cfg is only defined in RV64 (CSR[misa].MXL == 1)
Location

47:40

Description

PMP configuration for entry 61

The bits are as follows:

[separator="!",%autowidth]
!===
! Name ! Location ! Description

h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
h! - ! 46:45 ! Reserved Writes shall be ignored.
h! A ! 44:43
a! Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]

  • OFF (0) - Null region (disabled)

  • TOR (1) - Top of range

  • NA4 (2) - Naturally aligned four-byte region

  • NAPOT (3) - Natrually aligned power of two
    + [when="PMP_GRANULARITY >= 2"]

  • OFF (0) - Null region (disabled)

  • TOR (1) - Top of range

  • NAPOT (3) - Natrually aligned power of two

    [when="PMP_GRANULARITY >= 2"]
    Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

    h! X ! 42 ! When clear, instruction fetchs cause an Access Fault for the matching region and privilege mode.
    h! W ! 41 ! When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.
    h! R ! 40 ! When clear, loads cause an Access Fault for the matching region and privilege mode.
    !===

    The combination of R = 0, W = 1 is reserved.

Type
RW-R
RO
Reset value
UNDEFINED_LEGAL
0

pmp62cfg

pmp62cfg is only defined in RV64 (CSR[misa].MXL == 1)
Location

55:48

Description

PMP configuration for entry 62

The bits are as follows:

[separator="!",%autowidth]
!===
! Name ! Location ! Description

h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
h! - ! 54:53 ! Reserved Writes shall be ignored.
h! A ! 52:51
a! Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]

  • OFF (0) - Null region (disabled)

  • TOR (1) - Top of range

  • NA4 (2) - Naturally aligned four-byte region

  • NAPOT (3) - Natrually aligned power of two
    + [when="PMP_GRANULARITY >= 2"]

  • OFF (0) - Null region (disabled)

  • TOR (1) - Top of range

  • NAPOT (3) - Natrually aligned power of two

    [when="PMP_GRANULARITY >= 2"]
    Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

    h! X ! 50 ! When clear, instruction fetchs cause an Access Fault for the matching region and privilege mode.
    h! W ! 49 ! When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.
    h! R ! 48 ! When clear, loads cause an Access Fault for the matching region and privilege mode.
    !===

    The combination of R = 0, W = 1 is reserved.

Type
RW-R
RO
Reset value
UNDEFINED_LEGAL
0

pmp63cfg

pmp63cfg is only defined in RV64 (CSR[misa].MXL == 1)
Location

63:56

Description

PMP configuration for entry 63

The bits are as follows:

[separator="!",%autowidth]
!===
! Name ! Location ! Description

h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
h! - ! 62:61 ! Reserved Writes shall be ignored.
h! A ! 60:59
a! Address matching mode. One of:

[when="PMP_GRANULARITY < 2"]

  • OFF (0) - Null region (disabled)

  • TOR (1) - Top of range

  • NA4 (2) - Naturally aligned four-byte region

  • NAPOT (3) - Natrually aligned power of two
    + [when="PMP_GRANULARITY >= 2"]

  • OFF (0) - Null region (disabled)

  • TOR (1) - Top of range

  • NAPOT (3) - Natrually aligned power of two

    [when="PMP_GRANULARITY >= 2"]
    Naturally aligned four-byte region, NA4 (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).

    h! X ! 58 ! When clear, instruction fetchs cause an Access Fault for the matching region and privilege mode.
    h! W ! 57 ! When clear, stores and AMOs cause an Access Fault for the matching region and privilege mode.
    h! R ! 56 ! When clear, loads cause an Access Fault for the matching region and privilege mode.
    !===

    The combination of R = 0, W = 1 is reserved.

Type
RW-R
RO
Reset value
UNDEFINED_LEGAL
0

Software write

This CSR may store a value that is different from what software attempts to write.

When a software write occurs (e.g., through csrrw), the following determines the written value:

pmp56cfg = if ((CSR[pmpcfg14].pmp56cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp56cfg & 0x1) == 0) && ((csr_value.pmp56cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp56cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp56cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg14].pmp56cfg;

pmp57cfg = if ((CSR[pmpcfg14].pmp57cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp57cfg & 0x1) == 0) && ((csr_value.pmp57cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp57cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp57cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg14].pmp57cfg;

pmp58cfg = if ((CSR[pmpcfg14].pmp58cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp58cfg & 0x1) == 0) && ((csr_value.pmp58cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp58cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp58cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg14].pmp58cfg;

pmp59cfg = if ((CSR[pmpcfg14].pmp59cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp59cfg & 0x1) == 0) && ((csr_value.pmp59cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp59cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp59cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg14].pmp59cfg;

pmp60cfg = if ((CSR[pmpcfg14].pmp60cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp60cfg & 0x1) == 0) && ((csr_value.pmp60cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp60cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp60cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg14].pmp60cfg;

pmp61cfg = if ((CSR[pmpcfg14].pmp61cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp61cfg & 0x1) == 0) && ((csr_value.pmp61cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp61cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp61cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg14].pmp61cfg;

pmp62cfg = if ((CSR[pmpcfg14].pmp62cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp62cfg & 0x1) == 0) && ((csr_value.pmp62cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp62cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp62cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg14].pmp62cfg;

pmp63cfg = if ((CSR[pmpcfg14].pmp63cfg & 0x80) == 0) {
  # entry is not locked
  if (!(((csr_value.pmp63cfg & 0x1) == 0) && ((csr_value.pmp63cfg & 0x2) == 0x2))) {
    # not R = 0, W =1, which is reserved
    if ((PMP_GRANULARITY < 2) ||
        ((csr_value.pmp63cfg & 0x18) != 0x10)) {
      # NA4 is not allowed when PMP granularity is larger than 4 bytes
      return csr_value.pmp63cfg;
    }
  }
}
# fall through: keep old value
return CSR[pmpcfg14].pmp63cfg;